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[Qemu-ppc] [PULL 16/47] target/ppc: Add ibm, processor-radix-AP-encoding
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 16/47] target/ppc: Add ibm, processor-radix-AP-encodings for TCG |
Date: |
Mon, 24 Apr 2017 11:58:56 +1000 |
From: Suraj Jitindar Singh <address@hidden>
The ibm,processor-radix-AP-encodings device tree property of the cpu node
is used to specify the radix mode supported page sizes of the processor
to the guest os. Contained in the top 3 bits of the msb is the actual
page size (AP) encoding associated with the corresponding radix mode
supported page size. Add this property for a TCG guest, note the TCG code
is capable of translating any format so just add the 4 default page sizes.
The ibm,processor-radix-AP-encodings device tree property is defined as:
One to n cells in ascending order of radix mode supported page sizes
encoded as BE ints (32bit on ppc) in the form:
0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
- 0bxxx -> AP encoding
- 0byyyyyyyyyyyyyyyyyyyyyyyyyyyyy -> supported page size encoded as a shift
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/translate_init.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index c1a9014..aa0c44d 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -8808,6 +8808,25 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
}
+#ifdef CONFIG_SOFTMMU
+/*
+ * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
+ * Encoded as array of int_32s in the form:
+ * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
+ * x -> AP encoding
+ * y -> radix mode supported page size (encoded as a shift)
+ */
+static struct ppc_radix_page_info POWER9_radix_page_info = {
+ .count = 4,
+ .entries = {
+ 0x0000000c, /* 4K - enc: 0x0 */
+ 0xa0000010, /* 64K - enc: 0x5 */
+ 0x20000015, /* 2M - enc: 0x1 */
+ 0x4000001e /* 1G - enc: 0x2 */
+ }
+};
+#endif /* CONFIG_SOFTMMU */
+
static void init_proc_POWER9(CPUPPCState *env)
{
/* Common Registers */
@@ -8959,6 +8978,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
/* segment page size remain the same */
pcc->sps = &POWER7_POWER8_sps;
+ pcc->radix_page_info = &POWER9_radix_page_info;
#endif
pcc->excp_model = POWERPC_EXCP_POWER8;
pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
--
2.9.3
- [Qemu-ppc] [PULL 03/47] ppc/spapr: QOM'ify sPAPRRTCState, (continued)
- [Qemu-ppc] [PULL 03/47] ppc/spapr: QOM'ify sPAPRRTCState, David Gibson, 2017/04/23
- [Qemu-ppc] [PULL 06/47] spapr: Add ibm, processor-radix-AP-encodings to the device tree, David Gibson, 2017/04/23
- [Qemu-ppc] [PULL 05/47] target-ppc: kvm: make use of KVM_CREATE_SPAPR_TCE_64, David Gibson, 2017/04/23
- [Qemu-ppc] [PULL 14/47] spapr_pci: Warn when RAM page size is not enabled in IOMMU page mask, David Gibson, 2017/04/23
- [Qemu-ppc] [PULL 08/47] target/ppc: Add new H-CALL shells for in memory table translation, David Gibson, 2017/04/23
- [Qemu-ppc] [PULL 04/47] hw/ppc/pnv: Classify the "PowerNV Chip" devices as CPU devices, David Gibson, 2017/04/23
- [Qemu-ppc] [PULL 10/47] spapr: move spapr_populate_pa_features(), David Gibson, 2017/04/23
- [Qemu-ppc] [PULL 07/47] target-ppc: support KVM_CAP_PPC_MMU_RADIX, KVM_CAP_PPC_MMU_HASH_V3, David Gibson, 2017/04/23
- [Qemu-ppc] [PULL 15/47] spapr_pci: Removed unused include, David Gibson, 2017/04/23
- [Qemu-ppc] [PULL 09/47] target/ppc: Implement H_REGISTER_PROCESS_TABLE H_CALL, David Gibson, 2017/04/23
- [Qemu-ppc] [PULL 16/47] target/ppc: Add ibm, processor-radix-AP-encodings for TCG,
David Gibson <=
- [Qemu-ppc] [PULL 23/47] ppc/pnv: extend the machine with a InterruptStatsProvider interface, David Gibson, 2017/04/23
- [Qemu-ppc] [PULL 13/47] target-ppc/kvm: Enable in-kernel TCE acceleration for multi-tce, David Gibson, 2017/04/23
- [Qemu-ppc] [PULL 18/47] spapr: move the IRQ server number mapping under the machine, David Gibson, 2017/04/23
- [Qemu-ppc] [PULL 24/47] ppc/pnv: create the ICP object under PnvCore, David Gibson, 2017/04/23
- [Qemu-ppc] [PULL 29/47] ppc: add IPMI support, David Gibson, 2017/04/23
- [Qemu-ppc] [PULL 11/47] spapr: Enable ISA 3.0 MMU mode selection via CAS, David Gibson, 2017/04/23
- [Qemu-ppc] [PULL 12/47] spapr: Workaround for broken radix guests, David Gibson, 2017/04/23
- [Qemu-ppc] [PULL 20/47] ppc/xics: add a realize() handler to ICPStateClass, David Gibson, 2017/04/23
- [Qemu-ppc] [PULL 28/47] ppc/pnv: Add OCC model stub with interrupt support, David Gibson, 2017/04/23
- [Qemu-ppc] [PULL 40/47] ppc/pnv: populate device tree for serial devices, David Gibson, 2017/04/23