Re: [Qemu-ppc] MTTCG for ppc64 (removed from ppc-for-2.10)

[Nikunj A Dadhania]

David Gibson <address@hidden> writes:

> [ Unknown signature status ]
> Hi all,
>
> I'm afraid I've pulled the MTTCG enablement patches for target/ppc64
> out of my ppc-for-2.10 tree, since I discovered it was causing a
> repeatable failure on one of the Travis builds.
>
> Specifically, with both the LL/SC in terms of cmpxchg and
> enable-mttcg-by-default patches applied, and qemu build with clang,
> then make check will fail with a tcg_abort() in the powernv
> boot-serial test.

I see that in temp_load(), ts->val_type is ending up being
TEMP_VAL_DEAD, and the tcg_abort() is because of that.

Following patch gets past this error...

diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 4a1f24a..9a4ea5f 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3169,6 +3169,7 @@ static void gen_conditional_store(DisasContext *ctx, TCGv 
EA,
     tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
 
     t0 = tcg_temp_new();
+    tcg_gen_movi_tl(t0, 0);
     tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val,
                               cpu_gpr[reg], ctx->mem_idx,
                               DEF_MEMOP(memop) | MO_ALIGN);


.... but then stdcx. doesnt succeed, as the atomic_cmpxchg returns
0xFFFF.FFFF.FFFF.FFFF from the address(cpu_reserve) which does not match
the cpu_reserve_val(0). I am trying to trace what is the reason. Any
hints here would help.

Regards
Nikunj