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[Qemu-ppc] [PULL 13/17] target/ppc: Move no-execute and guarded page che
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 13/17] target/ppc: Move no-execute and guarded page checking into new function |
Date: |
Fri, 3 Mar 2017 14:25:03 +1100 |
From: Suraj Jitindar Singh <address@hidden>
A pte entry has bit fields which can be used to make a page no-execute or
guarded, if either of these bits are set then an instruction access to this
page will fail. Currently these bits are checked with the pp_prot function
however the ISA specifies that the access authority controlled by the
key-pp value pair should only be checked on an instruction access after
the no-execute and guard bits have already been verified to permit the
access.
Move the no-execute and guard bit checking into a new separate function.
Note that we can remove the check for the no-execute bit in the slb entry
since this check was already performed above when we obtained the slb
entry.
In the event that the no-execute or guard bits are set, an ISI should be
generated with the SRR1_NOEXEC_GUARD (0x10000000) bit set in srr1. Add a
define for this for clarity.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
[dwg: Move constants to cpu.h since they're not MMUv3 specific]
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/cpu.h | 1 +
target/ppc/mmu-hash64.c | 25 ++++++++++++++++---------
2 files changed, 17 insertions(+), 9 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 42fed6e..14c286e 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -475,6 +475,7 @@ struct ppc_slb_t {
/* SRR1 error code fields */
+#define SRR1_NOEXEC_GUARD 0x10000000
#define SRR1_PROTFAULT 0x08000000
#define SRR1_IAMR 0x00200000
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 99f936d..d985617 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -290,6 +290,16 @@ target_ulong helper_load_slb_vsid(CPUPPCState *env,
target_ulong rb)
return rt;
}
+/* Check No-Execute or Guarded Storage */
+static inline int ppc_hash64_pte_noexec_guard(PowerPCCPU *cpu,
+ ppc_hash_pte64_t pte)
+{
+ /* Exec permissions CANNOT take away read or write permissions */
+ return (pte.pte1 & HPTE64_R_N) || (pte.pte1 & HPTE64_R_G) ?
+ PAGE_READ | PAGE_WRITE : PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+}
+
+/* Check Basic Storage Protection */
static int ppc_hash64_pte_prot(PowerPCCPU *cpu,
ppc_slb_t *slb, ppc_hash_pte64_t pte)
{
@@ -333,12 +343,6 @@ static int ppc_hash64_pte_prot(PowerPCCPU *cpu,
}
}
- /* No execute if either noexec or guarded bits set */
- if (!(pte.pte1 & HPTE64_R_N) || (pte.pte1 & HPTE64_R_G)
- || (slb->vsid & SLB_VSID_N)) {
- prot |= PAGE_EXEC;
- }
-
return prot;
}
@@ -696,7 +700,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr
eaddr,
unsigned apshift;
hwaddr ptex;
ppc_hash_pte64_t pte;
- int pp_prot, amr_prot, prot;
+ int exec_prot, pp_prot, amr_prot, prot;
uint64_t new_pte1, dsisr;
const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC};
hwaddr raddr;
@@ -803,16 +807,19 @@ skip_slb_search:
/* 5. Check access permissions */
+ exec_prot = ppc_hash64_pte_noexec_guard(cpu, pte);
pp_prot = ppc_hash64_pte_prot(cpu, slb, pte);
amr_prot = ppc_hash64_amr_prot(cpu, pte);
- prot = pp_prot & amr_prot;
+ prot = exec_prot & pp_prot & amr_prot;
if ((need_prot[rwx] & ~prot) != 0) {
/* Access right violation */
qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n");
if (rwx == 2) {
int srr1 = 0;
- if (PAGE_EXEC & ~pp_prot) {
+ if (PAGE_EXEC & ~exec_prot) {
+ srr1 |= SRR1_NOEXEC_GUARD; /* Access violates noexec or guard
*/
+ } else if (PAGE_EXEC & ~pp_prot) {
srr1 |= SRR1_PROTFAULT; /* Access violates access authority */
}
if (PAGE_EXEC & ~amr_prot) {
--
2.9.3
- [Qemu-ppc] [PULL 10/17] hw/ppc/spapr: Add POWER9 to pseries cpu models, (continued)
- [Qemu-ppc] [PULL 10/17] hw/ppc/spapr: Add POWER9 to pseries cpu models, David Gibson, 2017/03/02
- [Qemu-ppc] [PULL 15/17] spapr_pci: Advertise access to PCIe extended config space, David Gibson, 2017/03/02
- [Qemu-ppc] [PULL 14/17] target/ppc: Rework hash mmu page fault code and add defines for clarity, David Gibson, 2017/03/02
- [Qemu-ppc] [PULL 07/17] target/ppc/POWER9: Add POWER9 mmu fault handler, David Gibson, 2017/03/02
- [Qemu-ppc] [PULL 06/17] target/ppc: Don't gen an SDR1 on POWER9 and rework register creation, David Gibson, 2017/03/02
- [Qemu-ppc] [PULL 01/17] target/ppc: Add POWER9/ISAv3.00 to compat_table, David Gibson, 2017/03/02
- [Qemu-ppc] [PULL 16/17] spapr: Small cleanup of PPC MMU enums, David Gibson, 2017/03/02
- [Qemu-ppc] [PULL 11/17] target/ppc: Add Instruction Authority Mask Register Check, David Gibson, 2017/03/02
- [Qemu-ppc] [PULL 13/17] target/ppc: Move no-execute and guarded page checking into new function,
David Gibson <=
- [Qemu-ppc] [PULL 05/17] target/ppc: Add patb_entry to sPAPRMachineState, David Gibson, 2017/03/02
- [Qemu-ppc] [PULL 17/17] target/ppc: rewrite f[n]m[add, sub] using float64_muladd, David Gibson, 2017/03/02
- [Qemu-ppc] [PULL 04/17] target/ppc/POWER9: Add POWERPC_MMU_V3 bit, David Gibson, 2017/03/02
- [Qemu-ppc] [PULL 03/17] powernv: Don't test POWER9 CPU yet, David Gibson, 2017/03/02
- [Qemu-ppc] [PULL 02/17] exec, kvm, target-ppc: Move getrampagesize() to common code, David Gibson, 2017/03/02
- [Qemu-ppc] [PULL 12/17] target/ppc: Add execute permission checking to access authority check, David Gibson, 2017/03/02
- [Qemu-ppc] [PULL 09/17] target/ppc/POWER9: Add cpu_has_work function for POWER9, David Gibson, 2017/03/02
- [Qemu-ppc] [PULL 08/17] target/ppc/POWER9: Add POWER9 pa-features definition, David Gibson, 2017/03/02
- Re: [Qemu-ppc] [Qemu-devel] [PULL 00/17] ppc-for-2.9 queue 20170303, no-reply, 2017/03/02