Re: [Qemu-ppc] [RFC NO-MERGE 09/12] target/ppc: Flush TLB on write to PIDR

[Suraj Jitindar Singh]

On Mon, 2017-02-20 at 13:18 +1100, David Gibson wrote:
> On Fri, Feb 17, 2017 at 04:08:09PM +1100, Suraj Jitindar Singh wrote:
> > 
> > The PIDR (process id register) is used to store the id of the
> > currently
> > running process, which is used to select the process table entry
> > used to
> > perform address translation. This means that when we write to this
> > register
> > all the translations in the TLB become outdated as they are for a
> > previously running process. Thus when this register is written to
> > we need
> > to invalidate the TLB entries to ensure stale entries aren't used
> > to
> > to perform translation for the new process, which would result in
> > at best
> > segfaults or alternatively just random memory being accessed.
> > 
> > Signed-off-by: Suraj Jitindar Singh <address@hidden>
> How does this interact with the SLB if running in hash mode without
> segment tables?  Does writing the PIDR automatically invalidate the
> SLB, or, does the SLB need to be invalidated separately?  If the
> second, then writing the PIDR probably doesn't need to invalidate the
> qemu TLB in hash+SLB mode.

Currently in hash we don't touch the pidr so it's a little irrelevant.
Entries are supposed to be automatically invalidated when the PIDR is
written to so I think we still need this since I don't believe the
software is required to issue an invalidation.

> 
> > 
> > ---
> >  target/ppc/helper.h         | 1 +
> >  target/ppc/misc_helper.c    | 8 ++++++++
> >  target/ppc/translate_init.c | 8 +++++++-
> >  3 files changed, 16 insertions(+), 1 deletion(-)
> > 
> > diff --git a/target/ppc/helper.h b/target/ppc/helper.h
> > index 85af9df..53ff749 100644
> > --- a/target/ppc/helper.h
> > +++ b/target/ppc/helper.h
> > @@ -698,6 +698,7 @@ DEF_HELPER_FLAGS_1(load_601_rtcu,
> > TCG_CALL_NO_RWG, tl, env)
> >  DEF_HELPER_FLAGS_1(load_purr, TCG_CALL_NO_RWG, tl, env)
> >  #endif
> >  DEF_HELPER_2(store_sdr1, void, env, tl)
> > +DEF_HELPER_2(store_pidr, void, env, tl)
> >  DEF_HELPER_FLAGS_2(store_tbl, TCG_CALL_NO_RWG, void, env, tl)
> >  DEF_HELPER_FLAGS_2(store_tbu, TCG_CALL_NO_RWG, void, env, tl)
> >  DEF_HELPER_FLAGS_2(store_atbl, TCG_CALL_NO_RWG, void, env, tl)
> > diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
> > index 49ba767..350057a 100644
> > --- a/target/ppc/misc_helper.c
> > +++ b/target/ppc/misc_helper.c
> > @@ -91,6 +91,14 @@ void helper_store_sdr1(CPUPPCState *env,
> > target_ulong val)
> >      }
> >  }
> >  
> > +void helper_store_pidr(CPUPPCState *env, target_ulong val)
> > +{
> > +    PowerPCCPU *cpu = ppc_env_get_cpu(env);
> > +
> > +    env->spr[SPR_BOOKS_PID] = val;
> > +    tlb_flush(CPU(cpu));
> > +}
> > +
> >  void helper_store_hid0_601(CPUPPCState *env, target_ulong val)
> >  {
> >      target_ulong hid0;
> > diff --git a/target/ppc/translate_init.c
> > b/target/ppc/translate_init.c
> > index 66a7f4a..bdc3894 100644
> > --- a/target/ppc/translate_init.c
> > +++ b/target/ppc/translate_init.c
> > @@ -394,6 +394,12 @@ static void spr_write_sdr1 (DisasContext *ctx,
> > int sprn, int gprn)
> >      gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
> >  }
> >  
> > +/* PIDR */
> > +static void spr_write_pidr (DisasContext *ctx, int sprn, int gprn)
> > +{
> > +    gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
> > +}
> > +
> >  /* 64 bits PowerPC specific SPRs */
> >  #if defined(TARGET_PPC64)
> >  static void spr_read_hior (DisasContext *ctx, int gprn, int sprn)
> > @@ -8170,7 +8176,7 @@ static void gen_spr_power8_book4(CPUPPCState
> > *env)
> >                       KVM_REG_PPC_ACOP, 0);
> >      spr_register_kvm(env, SPR_BOOKS_PID, "PID",
> >                       SPR_NOACCESS, SPR_NOACCESS,
> > -                     &spr_read_generic, &spr_write_generic,
> > +                     &spr_read_generic, &spr_write_pidr,
> >                       KVM_REG_PPC_PID, 0);
> >      spr_register_kvm(env, SPR_WORT, "WORT",
> >                       SPR_NOACCESS, SPR_NOACCESS,