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[Qemu-ppc] [PATCH v5 3/8] target/ppc: update ca32 in arithmetic substrac
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-ppc] [PATCH v5 3/8] target/ppc: update ca32 in arithmetic substract |
Date: |
Fri, 24 Feb 2017 11:16:39 +0530 |
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target/ppc/translate.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index eba83ef..e083082 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -827,7 +827,11 @@ static inline void gen_op_arith_compute_ca32(DisasContext
*ctx,
}
t0 = tcg_temp_new();
- tcg_gen_xor_tl(t0, arg0, arg1);
+ if (sub) {
+ tcg_gen_eqv_tl(t0, arg0, arg1);
+ } else {
+ tcg_gen_xor_tl(t0, arg0, arg1);
+ }
tcg_gen_xor_tl(t0, t0, res);
tcg_gen_extract_tl(cpu_ca32, t0, 32, 1);
tcg_temp_free(t0);
@@ -1378,17 +1382,22 @@ static inline void gen_op_arith_subf(DisasContext *ctx,
TCGv ret, TCGv arg1,
tcg_temp_free(t1);
tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
+ if (is_isa300(ctx)) {
+ tcg_gen_mov_tl(cpu_ca32, cpu_ca);
+ }
} else if (add_ca) {
TCGv zero, inv1 = tcg_temp_new();
tcg_gen_not_tl(inv1, arg1);
zero = tcg_const_tl(0);
tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
+ gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, 0);
tcg_temp_free(zero);
tcg_temp_free(inv1);
} else {
tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
tcg_gen_sub_tl(t0, arg2, arg1);
+ gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 1);
}
} else if (add_ca) {
/* Since we're ignoring carry-out, we can simplify the
--
2.7.4
- [Qemu-ppc] [PATCH v5 0/8] POWER9 TCG enablements - part15, Nikunj A Dadhania, 2017/02/24
- [Qemu-ppc] [PATCH v5 2/8] target/ppc: update ca32 in arithmetic add, Nikunj A Dadhania, 2017/02/24
- [Qemu-ppc] [PATCH v5 1/8] target/ppc: support for 32-bit carry and overflow, Nikunj A Dadhania, 2017/02/24
- [Qemu-ppc] [PATCH v5 3/8] target/ppc: update ca32 in arithmetic substract,
Nikunj A Dadhania <=
- [Qemu-ppc] [PATCH v5 4/8] target/ppc: update overflow flags for add/sub, Nikunj A Dadhania, 2017/02/24
- [Qemu-ppc] [PATCH v5 6/8] target/ppc: add ov32 flag for multiply low insns, Nikunj A Dadhania, 2017/02/24
- [Qemu-ppc] [PATCH v5 8/8] target/ppc: add mcrxrx instruction, Nikunj A Dadhania, 2017/02/24
- [Qemu-ppc] [PATCH v5 5/8] target/ppc: use tcg ops for neg instruction, Nikunj A Dadhania, 2017/02/24
- [Qemu-ppc] [PATCH v5 7/8] target/ppc: add ov32 flag in divide operations, Nikunj A Dadhania, 2017/02/24