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[Qemu-ppc] [PATCH v2 00/11] POWER9 TCG enablements - part15
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-ppc] [PATCH v2 00/11] POWER9 TCG enablements - part15 |
Date: |
Wed, 22 Feb 2017 14:59:37 +0530 |
This series contains implentation of CA32 and OV32 bits added to the
ISA 3.0. Various fixed-point arithmetic instructions are updated to take
care of the newer flags.
Finally the last patch adds new instruction mcrxrx, that helps reading
the carry (CA and CA32) and the overflow (OV and OV32) flags
Changelog:
v1:
* Use these ISA 3.0 flag to enable CA32 and OV32
* Re-write ca32 compute routine
* Add setting of flags for "neg." and "nego."
Nikunj A Dadhania (11):
target/ppc: move cpu_[read, write]_xer to cpu.c
target/ppc: optimize gen_write_xer()
target/ppc: support for 32-bit carry and overflow
target/ppc: update ca32 in arithmetic add
target/ppc: update ca32 in arithmetic substract
target/ppc: update overflow flags for add/sub
target/ppc: use tcg ops for neg instruction
target/ppc: update ov/ov32 for nego
target/ppc: add ov32 flag for multiply low insns
target/ppc: add ov32 flag in divide operations
target/ppc: add mcrxrx instruction
target/ppc/Makefile.objs | 1 +
target/ppc/cpu.c | 51 ++++++++++++++++
target/ppc/cpu.h | 21 +++----
target/ppc/int_helper.c | 49 +++++----------
target/ppc/translate.c | 143 ++++++++++++++++++++++++++++++++++++--------
target/ppc/translate_init.c | 4 +-
6 files changed, 196 insertions(+), 73 deletions(-)
create mode 100644 target/ppc/cpu.c
--
2.7.4
- [Qemu-ppc] [PATCH v2 00/11] POWER9 TCG enablements - part15,
Nikunj A Dadhania <=