Re: [Qemu-ppc] [PATCH 5/6] target-ppc: support for 32-bit carry and overflow

[David Gibson]

On Thu, Feb 09, 2017 at 04:04:04PM +0530, Nikunj A Dadhania wrote:
> POWER ISA 3.0 adds CA32 and OV32 status in 64-bit mode. Add the flags
> and corresponding defines. Moreover, CA32 is set when CA is set and
> OV32 is set when OV is set, there is no need to have a new
> fields in the CPUPPCState structure.
> 
> Signed-off-by: Nikunj A Dadhania <address@hidden>

Um.. I don't quite understand this.  If CA always has the same value
as CA32, what's the point?

> ---
>  target/ppc/cpu.h       | 26 ++++++++++++++++++++++++++
>  target/ppc/translate.c |  6 ++++++
>  2 files changed, 32 insertions(+)
> 
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index bc2a2ce..181919b 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1354,11 +1354,15 @@ int ppc_compat_max_threads(PowerPCCPU *cpu);
>  #define XER_SO  31
>  #define XER_OV  30
>  #define XER_CA  29
> +#define XER_OV32  19
> +#define XER_CA32  18
>  #define XER_CMP  8
>  #define XER_BC   0
>  #define xer_so  (env->so)
>  #define xer_ov  (env->ov)
>  #define xer_ca  (env->ca)
> +#define xer_ov32  (env->ov)
> +#define xer_ca32  (env->ca)
>  #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
>  #define xer_bc  ((env->xer >> XER_BC)  & 0x7F)
>  
> @@ -2325,11 +2329,21 @@ enum {
>  
>  
> /*****************************************************************************/
>  
> +#ifndef TARGET_PPC64
>  static inline target_ulong cpu_read_xer(CPUPPCState *env)
>  {
>      return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) | (env->ca 
> << XER_CA);
>  }
> +#else
> +static inline target_ulong cpu_read_xer(CPUPPCState *env)
> +{
> +    return env->xer | (env->so << XER_SO) |
> +        (env->ov << XER_OV) | (env->ca << XER_CA) |
> +        (env->ov << XER_OV32) | (env->ca << XER_CA32);
> +}
> +#endif
>  
> +#ifndef TARGET_PPC64
>  static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer)
>  {
>      env->so = (xer >> XER_SO) & 1;
> @@ -2337,6 +2351,18 @@ static inline void cpu_write_xer(CPUPPCState *env, 
> target_ulong xer)
>      env->ca = (xer >> XER_CA) & 1;
>      env->xer = xer & ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA));
>  }
> +#else
> +static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer)
> +{
> +    env->so = (xer >> XER_SO) & 1;
> +    env->ov = ((xer >> XER_OV) & 1) | ((xer >> XER_OV32) & 1);
> +    env->ca = ((xer >> XER_CA) & 1) | ((xer >> XER_CA32) & 1);
> +    env->xer = xer & ~((1ul << XER_SO) |
> +                       (1ul << XER_OV) | (1ul << XER_CA) |
> +                       (1ul << XER_OV32) | (1ul << XER_CA32));
> +}
> +#endif
> +
>  
>  static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
>                                          target_ulong *cs_base, uint32_t 
> *flags)
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 3ba2616..724ad17 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -3715,6 +3715,12 @@ static void gen_read_xer(TCGv dst)
>      tcg_gen_or_tl(t0, t0, t1);
>      tcg_gen_or_tl(dst, dst, t2);
>      tcg_gen_or_tl(dst, dst, t0);
> +#ifdef TARGET_PPC64
> +    tcg_gen_shli_tl(t0, cpu_ov, XER_OV32);
> +    tcg_gen_or_tl(dst, dst, t0);
> +    tcg_gen_shli_tl(t0, cpu_ca, XER_CA32);
> +    tcg_gen_or_tl(dst, dst, t0);
> +#endif
>      tcg_temp_free(t0);
>      tcg_temp_free(t1);
>      tcg_temp_free(t2);

-- 
David Gibson                    | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
                                | _way_ _around_!
http://www.ozlabs.org/~dgibson

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