Re: [Qemu-ppc] [Qemu-devel] [PULL 000/107] ppc-for-2.9 queue 20170202

[no-reply]

Hi,

Your series seems to have some coding style problems. See output below for
more information:

Type: series
Subject: [Qemu-devel] [PULL 000/107] ppc-for-2.9 queue 20170202
Message-id: address@hidden

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

# Useful git options
git config --local diff.renamelimit 0
git config --local diff.renames True

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
    echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
    if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
        failed=1
        echo
    fi
    n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag]         patchew/address@hidden -> patchew/address@hidden
Switched to a new branch 'test'
35804eb hw/ppc/pnv: Use error_report instead of hw_error if a ROM file can't be 
found
553383c ppc/kvm: Handle the "family" CPU via alias instead of registering new 
types
fff00af target/ppc/mmu_hash64: Fix incorrect shift value in amr calculation
60cd504 target/ppc/mmu_hash64: Fix printing unsigned as signed int
46acfe8 tcg/POWER9: NOOP the cp_abort instruction
8d6a4ad target/ppc/debug: Print LPCR register value if register exists
f6f6058 target-ppc: Add xststdc[sp, dp, qp] instructions
f58f163 target-ppc: Add xvtstdc[sp, dp] instructions
b5846c9 target-ppc: Add MMU model check for booke machines
bf44c52 ppc: switch to constants within BUILD_BUG_ON
91a98de target/ppc/cpu-models: Fix/remove bad CPU aliases
1507ee8 target/ppc: Remove unused POWERPC_FAMILY(POWER)
9ed06de spapr: clock should count only if vm is running
6aa2555 ppc: Remove unused function cpu_ppc601_rtc_init()
e4aa91a target/ppc: Add pcr_supported to POWER9 cpu class definition
3089ebb powerpc/cpu-models: rename ISAv3.00 logical PVR definition
1cec41f target-ppc: Add xvcv[hpsp, sphp] instructions
3517029 target-ppc: Add xsmulqp instruction
5a8f66a target-ppc: Add xsdivqp instruction
a9bb0d1 target-ppc: Add xscvsdqp and xscvudqp instructions
9a52378 target-ppc: Use ppc_vsr_t.f128 in xscmp[o, u, exp]qp
72f4fed ppc: Implement bcdutrunc. instruction
6c0e217 ppc: Implement bcdtrunc. instruction
7ca15f3 ppc/prep: update MAINTAINERS file
8d5ce9f target-ppc: Add xscvqps[d, w]z instructions
bd7ad88 target-ppc: Add xvxsigdp instruction
d267b01 target-ppc: Add xvxsigsp instruction
ac1c4c8 target-ppc: Add xvxexpdp instruction
e54f555 target-ppc: Add xvxexpsp instruction
957481d target-ppc: Add xviexpdp instruction
1a2ad11 target-ppc: Add xviexpsp instruction
96b7336 target-ppc: Add xsiexpqp instruction
42fc40e target-ppc: Add xsiexpdp instruction
de437b9 ppc: Implement bcdsr. instruction
7d5bb5b ppc: Implement bcdus. instruction
78c1f6e ppc: Implement bcds. instruction
3056a60 host-utils: Implement unsigned quadword left/right shift and unit tests
06e81ce host-utils: Move 128-bit guard macro to .c file
4bc7891 softfloat: Fix the default qNAN for target-ppc
0434c20 target-ppc: xscvqpdp zero VSR
aa035c2 ppc: Fix a warning in bcdcfz code and improve BCD_DIG_BYTE macro
556497f ppc: Prevent inifnite loop in decrementer auto-reload.
e012dbc target-ppc: Add xscvqpdp instruction
8d8a981 target-ppc: Add xscvdpqp instruction
f1d5111 target-ppc: Add xsaddqp instructions
1f9299e ppc: Add ppc_set_compat_all()
fb7d777 pseries: Rewrite CAS PVR compatibility logic
674995f pxb: Restrict to x86
ef2c351 target-ppc: Add xsxsigqp instructions
12334a6 target-ppc: Add xsxsigdp instruction
f925e81 target-ppc: Add xsxexpqp instruction
d3141f1 target-ppc: Add xsxexpdp instruction
326780e target-ppc: Use correct precision for FPRF setting
ede2edc target-ppc: Add xscvdphp, xscvhpdp
deef0f5 target-ppc: Rename helper_compute_fprf to helper_compute_fprf_float64
557d243 target-ppc: Replace isden by float64_is_zero_or_denormal
08939e4 target-ppc: Use float64 arg in helper_compute_fprf()
105ef41 prep: add IBM RS/6000 7020 (40p) machine emulation
0cfc825 prep: add IBM RS/6000 7020 (40p) memory controller
5cabcfb prep: add PReP System I/O
057434d target-ppc: Add xxinsertw instruction
a32b6d5 target-ppc: Add xxextractuw instruction
46f8417 hw/ppc: QOM'ify spapr_vio.c
5c3a831 hw/ppc: QOM'ify ppce500_spin.c
aed5da0 hw/ppc: QOM'ify e500.c
e9570a2 hw/gpio: QOM'ify mpc8xxx.c
78ddd8b qtest: add ivshmem-test for ppc64
e9e79b4 qtest: convert ivshmem-test to use libqos
73cf015 libqos: fix spapr qpci_map()
7551389 qtest: add display-vga-test to ppc64
0eb86ff qtest: add netfilter tests for ppc64
1c16d80 ppc: Validate compatibility modes when setting
f07a736 ppc: Rewrite ppc_get_compat_smt_threads()
22c116b ppc: Rewrite ppc_set_compat()
4abde08 pseries: Add pseries-2.9 machine type
e5d5fe6 prep: do not use global variable to access nvram
b264732 hw/ppc/spapr: Fix boot path of usb-host storage devices
77413e4 target-ppc: implement stxvll instructions
6dbc344 target-ppc: implement stxvl instruction
1596aa7 target-ppc: implement lxvll instruction
92c18ab target-ppc: implement lxvl instruction
586e4a5 target-ppc: Add xxperm and xxpermr instructions
d3de434 target-ppc: implement xscpsgnqp instruction
225270b target-ppc: implement xsnegqp instruction
b94b1ae target-ppc: Implement bcd_is_valid function
9be9692 target-ppc: implement xsabsqp/xsnabsqp instruction
e50ee80 target-ppc: implement stop instruction
92d33d4 target-ppc: move ppc_vsr_t to common header
fd23c4c ppc/spapr: implement H_SIGNAL_SYS_RESET
5fb68f7 ppc: Rename cpu_version to compat_pvr
6a7600c ppc: Clean up and QOMify hypercall emulation
f61f986 pseries: Make cpu_update during CAS unconditional
78cc6be pseries: Always use core objects for CPU construction
f588f36 target-ppc: add vextu[bhw][lr]x instructions
e110bec target-ppc: Implement bcdsetsgn. instruction
f16a6c0 target-ppc: Implement bcdcpsgn. instruction
a7bfc23 target-ppc: Implement bcdctsq. instruction
e8cfa54 target-ppc: Implement bcdcfsq. instruction
683c4bc target-ppc: implement lxv/lxvx and stxv/stxvx
1d926ac target-ppc: implement stxsd and stxssp
6e3ce97 target-ppc: implement lxsd and lxssp instructions
21703ef target-ppc: Add xscmpoqp and xscmpuqp instructions
c0e1d8f target-ppc: Add xscmpexp[dp, qp] instructions
269c965 target-ppc: Fix xscmpodp and xscmpudp instructions
6aeab51 target-ppc: rename CRF_* defines as CRF_*_BIT
e2d65e3 target-ppc: Consolidate instruction decode helpers
18b98fb disas/ppc: Fix indefinite articles in comments

=== OUTPUT BEGIN ===
Checking PATCH 1/107: disas/ppc: Fix indefinite articles in comments...
Checking PATCH 2/107: target-ppc: Consolidate instruction decode helpers...
Checking PATCH 3/107: target-ppc: rename CRF_* defines as CRF_*_BIT...
Checking PATCH 4/107: target-ppc: Fix xscmpodp and xscmpudp instructions...
Checking PATCH 5/107: target-ppc: Add xscmpexp[dp, qp] instructions...
Checking PATCH 6/107: target-ppc: Add xscmpoqp and xscmpuqp instructions...
Checking PATCH 7/107: target-ppc: implement lxsd and lxssp instructions...
Checking PATCH 8/107: target-ppc: implement stxsd and stxssp...
Checking PATCH 9/107: target-ppc: implement lxv/lxvx and stxv/stxvx...
Checking PATCH 10/107: target-ppc: Implement bcdcfsq. instruction...
Checking PATCH 11/107: target-ppc: Implement bcdctsq. instruction...
Checking PATCH 12/107: target-ppc: Implement bcdcpsgn. instruction...
Checking PATCH 13/107: target-ppc: Implement bcdsetsgn. instruction...
Checking PATCH 14/107: target-ppc: add vextu[bhw][lr]x instructions...
Checking PATCH 15/107: pseries: Always use core objects for CPU construction...
Checking PATCH 16/107: pseries: Make cpu_update during CAS unconditional...
Checking PATCH 17/107: ppc: Clean up and QOMify hypercall emulation...
Checking PATCH 18/107: ppc: Rename cpu_version to compat_pvr...
Checking PATCH 19/107: ppc/spapr: implement H_SIGNAL_SYS_RESET...
Checking PATCH 20/107: target-ppc: move ppc_vsr_t to common header...
Checking PATCH 21/107: target-ppc: implement stop instruction...
Checking PATCH 22/107: target-ppc: implement xsabsqp/xsnabsqp instruction...
Checking PATCH 23/107: target-ppc: Implement bcd_is_valid function...
Checking PATCH 24/107: target-ppc: implement xsnegqp instruction...
Checking PATCH 25/107: target-ppc: implement xscpsgnqp instruction...
Checking PATCH 26/107: target-ppc: Add xxperm and xxpermr instructions...
Checking PATCH 27/107: target-ppc: implement lxvl instruction...
Checking PATCH 28/107: target-ppc: implement lxvll instruction...
Checking PATCH 29/107: target-ppc: implement stxvl instruction...
Checking PATCH 30/107: target-ppc: implement stxvll instructions...
Checking PATCH 31/107: hw/ppc/spapr: Fix boot path of usb-host storage 
devices...
Checking PATCH 32/107: prep: do not use global variable to access nvram...
Checking PATCH 33/107: pseries: Add pseries-2.9 machine type...
Checking PATCH 34/107: ppc: Rewrite ppc_set_compat()...
Checking PATCH 35/107: ppc: Rewrite ppc_get_compat_smt_threads()...
Checking PATCH 36/107: ppc: Validate compatibility modes when setting...
Checking PATCH 37/107: qtest: add netfilter tests for ppc64...
Checking PATCH 38/107: qtest: add display-vga-test to ppc64...
Checking PATCH 39/107: libqos: fix spapr qpci_map()...
Checking PATCH 40/107: qtest: convert ivshmem-test to use libqos...
Checking PATCH 41/107: qtest: add ivshmem-test for ppc64...
Checking PATCH 42/107: hw/gpio: QOM'ify mpc8xxx.c...
Checking PATCH 43/107: hw/ppc: QOM'ify e500.c...
Checking PATCH 44/107: hw/ppc: QOM'ify ppce500_spin.c...
Checking PATCH 45/107: hw/ppc: QOM'ify spapr_vio.c...
Checking PATCH 46/107: target-ppc: Add xxextractuw instruction...
ERROR: Macros with complex values should be enclosed in parenthesis
#110: FILE: target/ppc/translate/vsx-ops.inc.c:52:
+#define GEN_XX2FORM_EXT(name, opc2, opc3, fl2)                          \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0x00100000, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0x00100000, PPC_NONE, fl2)

total: 1 errors, 0 warnings, 92 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 47/107: target-ppc: Add xxinsertw instruction...
Checking PATCH 48/107: prep: add PReP System I/O...
Checking PATCH 49/107: prep: add IBM RS/6000 7020 (40p) memory controller...
Checking PATCH 50/107: prep: add IBM RS/6000 7020 (40p) machine emulation...
Checking PATCH 51/107: target-ppc: Use float64 arg in helper_compute_fprf()...
Checking PATCH 52/107: target-ppc: Replace isden by 
float64_is_zero_or_denormal...
Checking PATCH 53/107: target-ppc: Rename helper_compute_fprf to 
helper_compute_fprf_float64...
Checking PATCH 54/107: target-ppc: Add xscvdphp, xscvhpdp...
Checking PATCH 55/107: target-ppc: Use correct precision for FPRF setting...
Checking PATCH 56/107: target-ppc: Add xsxexpdp instruction...
Checking PATCH 57/107: target-ppc: Add xsxexpqp instruction...
Checking PATCH 58/107: target-ppc: Add xsxsigdp instruction...
Checking PATCH 59/107: target-ppc: Add xsxsigqp instructions...
Checking PATCH 60/107: pxb: Restrict to x86...
Checking PATCH 61/107: pseries: Rewrite CAS PVR compatibility logic...
Checking PATCH 62/107: ppc: Add ppc_set_compat_all()...
Checking PATCH 63/107: target-ppc: Add xsaddqp instructions...
Checking PATCH 64/107: target-ppc: Add xscvdpqp instruction...
Checking PATCH 65/107: target-ppc: Add xscvqpdp instruction...
Checking PATCH 66/107: ppc: Prevent inifnite loop in decrementer auto-reload....
Checking PATCH 67/107: ppc: Fix a warning in bcdcfz code and improve 
BCD_DIG_BYTE macro...
Checking PATCH 68/107: target-ppc: xscvqpdp zero VSR...
Checking PATCH 69/107: softfloat: Fix the default qNAN for target-ppc...
Checking PATCH 70/107: host-utils: Move 128-bit guard macro to .c file...
Checking PATCH 71/107: host-utils: Implement unsigned quadword left/right shift 
and unit tests...
Checking PATCH 72/107: ppc: Implement bcds. instruction...
Checking PATCH 73/107: ppc: Implement bcdus. instruction...
Checking PATCH 74/107: ppc: Implement bcdsr. instruction...
Checking PATCH 75/107: target-ppc: Add xsiexpdp instruction...
Checking PATCH 76/107: target-ppc: Add xsiexpqp instruction...
Checking PATCH 77/107: target-ppc: Add xviexpsp instruction...
Checking PATCH 78/107: target-ppc: Add xviexpdp instruction...
Checking PATCH 79/107: target-ppc: Add xvxexpsp instruction...
Checking PATCH 80/107: target-ppc: Add xvxexpdp instruction...
Checking PATCH 81/107: target-ppc: Add xvxsigsp instruction...
Checking PATCH 82/107: target-ppc: Add xvxsigdp instruction...
Checking PATCH 83/107: target-ppc: Add xscvqps[d, w]z instructions...
Checking PATCH 84/107: ppc/prep: update MAINTAINERS file...
Checking PATCH 85/107: ppc: Implement bcdtrunc. instruction...
Checking PATCH 86/107: ppc: Implement bcdutrunc. instruction...
Checking PATCH 87/107: target-ppc: Use ppc_vsr_t.f128 in xscmp[o, u, exp]qp...
Checking PATCH 88/107: target-ppc: Add xscvsdqp and xscvudqp instructions...
Checking PATCH 89/107: target-ppc: Add xsdivqp instruction...
Checking PATCH 90/107: target-ppc: Add xsmulqp instruction...
Checking PATCH 91/107: target-ppc: Add xvcv[hpsp, sphp] instructions...
Checking PATCH 92/107: powerpc/cpu-models: rename ISAv3.00 logical PVR 
definition...
Checking PATCH 93/107: target/ppc: Add pcr_supported to POWER9 cpu class 
definition...
ERROR: spaces required around that '-' (ctx:VxV)
#22: FILE: target/ppc/cpu.h:2293:
+    PCR_COMPAT_3_00     = 1ull << (63-59),
                                      ^

total: 1 errors, 0 warnings, 15 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 94/107: ppc: Remove unused function cpu_ppc601_rtc_init()...
Checking PATCH 95/107: spapr: clock should count only if vm is running...
Checking PATCH 96/107: target/ppc: Remove unused POWERPC_FAMILY(POWER)...
Checking PATCH 97/107: target/ppc/cpu-models: Fix/remove bad CPU aliases...
Checking PATCH 98/107: ppc: switch to constants within BUILD_BUG_ON...
Checking PATCH 99/107: target-ppc: Add MMU model check for booke machines...
Checking PATCH 100/107: target-ppc: Add xvtstdc[sp, dp] instructions...
ERROR: Macros with complex values should be enclosed in parenthesis
#126: FILE: target/ppc/translate/vsx-ops.inc.c:137:
+#define GEN_XX2FORM_DCMX(name, opc2, opc3, fl2) \
+GEN_XX3FORM(name, opc2, opc3 | 0, fl2),         \
+GEN_XX3FORM(name, opc2, opc3 | 1, fl2)

total: 1 errors, 0 warnings, 96 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 101/107: target-ppc: Add xststdc[sp, dp, qp] instructions...
Checking PATCH 102/107: target/ppc/debug: Print LPCR register value if register 
exists...
Checking PATCH 103/107: tcg/POWER9: NOOP the cp_abort instruction...
ERROR: do not use C99 // comments
#28: FILE: target/ppc/translate.c:6025:
+    // Do Nothing

total: 1 errors, 0 warnings, 17 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 104/107: target/ppc/mmu_hash64: Fix printing unsigned as signed 
int...
Checking PATCH 105/107: target/ppc/mmu_hash64: Fix incorrect shift value in amr 
calculation...
Checking PATCH 106/107: ppc/kvm: Handle the "family" CPU via alias instead of 
registering new types...
Checking PATCH 107/107: hw/ppc/pnv: Use error_report instead of hw_error if a 
ROM file can't be found...
=== OUTPUT END ===

Test command exited with code: 1


---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to address@hidden