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[Qemu-ppc] [PATCH v2 1/2] target-ppc: add vextu[bhw]lx instructions
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From: |
Nikunj A Dadhania |
|
Subject: |
[Qemu-ppc] [PATCH v2 1/2] target-ppc: add vextu[bhw]lx instructions |
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Date: |
Thu, 24 Nov 2016 17:02:43 +0530 |
From: Avinesh Kumar <address@hidden>
vextublx: Vector Extract Unsigned Byte Left
vextuhlx: Vector Extract Unsigned Halfword Left
vextuwlx: Vector Extract Unsigned Word Left
Signed-off-by: Avinesh Kumar <address@hidden>
[ implement using int128_rshift ]
Signed-off-by: Nikunj A Dadhania <address@hidden>
---
target-ppc/helper.h | 3 +++
target-ppc/int_helper.c | 48 +++++++++++++++++++++++++++++++++++++
target-ppc/translate/vmx-impl.inc.c | 18 ++++++++++++++
target-ppc/translate/vmx-ops.inc.c | 4 +++-
4 files changed, 72 insertions(+), 1 deletion(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 3b26678..d0a8fb2 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -366,6 +366,9 @@ DEF_HELPER_3(vpmsumb, void, avr, avr, avr)
DEF_HELPER_3(vpmsumh, void, avr, avr, avr)
DEF_HELPER_3(vpmsumw, void, avr, avr, avr)
DEF_HELPER_3(vpmsumd, void, avr, avr, avr)
+DEF_HELPER_2(vextublx, tl, tl, avr)
+DEF_HELPER_2(vextuhlx, tl, tl, avr)
+DEF_HELPER_2(vextuwlx, tl, tl, avr)
DEF_HELPER_2(vsbox, void, avr, avr)
DEF_HELPER_3(vcipher, void, avr, avr, avr)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index fbf477f..2aa4474 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -17,6 +17,7 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
+#include "qemu/int128.h"
#include "cpu.h"
#include "internal.h"
#include "exec/exec-all.h"
@@ -1805,6 +1806,53 @@ void helper_vlogefp(CPUPPCState *env, ppc_avr_t *r,
ppc_avr_t *b)
}
}
+#if defined(HOST_WORDS_BIGENDIAN)
+# if defined(CONFIG_INT128)
+# define VEXTULX_DO(name, size) \
+ target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b) \
+ { \
+ int index = (a & 0xf) * 8; \
+ return int128_rshift(b->u128, index) & \
+ MAKE_64BIT_MASK(0, size); \
+ }
+# else
+# define VEXTULX_DO(name, size) \
+ target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b) \
+ { \
+ int index = (a & 0xf) * 8; \
+ Int128 value = int128_make128(b->u64[LO_IDX], \
+ b->u64[HI_IDX]); \
+ return int128_rshift(value, index) & \
+ MAKE_64BIT_MASK(0, size); \
+ }
+# endif
+#else
+# if defined(CONFIG_INT128)
+# define VEXTULX_DO(name, size) \
+ target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b) \
+ { \
+ int index = (15 - (a & 0xf) + 1) * 8; \
+ return int128_rshift(b->u128, index - size) & \
+ MAKE_64BIT_MASK(0, size); \
+ }
+# else
+# define VEXTULX_DO(name, size) \
+ target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b) \
+ { \
+ int index = (15 - (a & 0xf) + 1) * 8; \
+ Int128 value = int128_make128(b->u64[LO_IDX], \
+ b->u64[HI_IDX]); \
+ return int128_rshift(value, index - size) & \
+ MAKE_64BIT_MASK(0, size); \
+ }
+# endif
+#endif
+
+VEXTULX_DO(vextublx, 8)
+VEXTULX_DO(vextuhlx, 16)
+VEXTULX_DO(vextuwlx, 32)
+#undef VEXTULX_DO
+
/* The specification says that the results are undefined if all of the
* shift counts are not identical. We check to make sure that they are
* to conform to what real hardware appears to do. */
diff --git a/target-ppc/translate/vmx-impl.inc.c
b/target-ppc/translate/vmx-impl.inc.c
index 7143eb3..e91d10b 100644
--- a/target-ppc/translate/vmx-impl.inc.c
+++ b/target-ppc/translate/vmx-impl.inc.c
@@ -340,6 +340,19 @@ static void glue(gen_, name0##_##name1)(DisasContext *ctx)
\
} \
}
+#define GEN_VXFORM_HETRO(name, opc2, opc3) \
+static void glue(gen_, name)(DisasContext *ctx) \
+{ \
+ TCGv_ptr rb; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ rb = gen_avr_ptr(rB(ctx->opcode)); \
+ gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], rb);
\
+ tcg_temp_free_ptr(rb); \
+}
+
GEN_VXFORM(vaddubm, 0, 0);
GEN_VXFORM_DUAL_EXT(vaddubm, PPC_ALTIVEC, PPC_NONE, 0, \
vmul10cuq, PPC_NONE, PPC2_ISA300, 0x0000F800)
@@ -525,6 +538,11 @@ GEN_VXFORM_ENV(vaddfp, 5, 0);
GEN_VXFORM_ENV(vsubfp, 5, 1);
GEN_VXFORM_ENV(vmaxfp, 5, 16);
GEN_VXFORM_ENV(vminfp, 5, 17);
+GEN_VXFORM_HETRO(vextublx, 6, 24)
+GEN_VXFORM_HETRO(vextuhlx, 6, 25)
+GEN_VXFORM_HETRO(vextuwlx, 6, 26)
+GEN_VXFORM_DUAL(vmrgow, PPC_NONE, PPC2_ALTIVEC_207,
+ vextuwlx, PPC_NONE, PPC2_ISA300)
#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
static void glue(gen_, name)(DisasContext *ctx) \
diff --git a/target-ppc/translate/vmx-ops.inc.c
b/target-ppc/translate/vmx-ops.inc.c
index f02b3be..e62e564 100644
--- a/target-ppc/translate/vmx-ops.inc.c
+++ b/target-ppc/translate/vmx-ops.inc.c
@@ -91,8 +91,10 @@ GEN_VXFORM(vmrghw, 6, 2),
GEN_VXFORM(vmrglb, 6, 4),
GEN_VXFORM(vmrglh, 6, 5),
GEN_VXFORM(vmrglw, 6, 6),
+GEN_VXFORM_300(vextublx, 6, 24),
+GEN_VXFORM_300(vextuhlx, 6, 25),
+GEN_VXFORM_DUAL(vmrgow, vextuwlx, 6, 26, PPC_NONE, PPC2_ALTIVEC_207),
GEN_VXFORM_207(vmrgew, 6, 30),
-GEN_VXFORM_207(vmrgow, 6, 26),
GEN_VXFORM(vmuloub, 4, 0),
GEN_VXFORM(vmulouh, 4, 1),
GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
--
2.7.4