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[Qemu-ppc] [PULL 15/19] ppc/pnv: add a 'xscom_core_base' field to PnvChi
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 15/19] ppc/pnv: add a 'xscom_core_base' field to PnvChipClass |
Date: |
Tue, 15 Nov 2016 13:49:00 +1100 |
From: Cédric Le Goater <address@hidden>
The XSCOM addresses for the core registers are encoded in a slightly
different way on POWER8 and POWER9.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/ppc/pnv.c | 8 +++++++-
include/hw/ppc/pnv.h | 1 +
include/hw/ppc/pnv_xscom.h | 5 ++---
3 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 6af3424..e777958 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -521,6 +521,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass,
void *data)
k->cores_mask = POWER8E_CORE_MASK;
k->core_pir = pnv_chip_core_pir_p8;
k->xscom_base = 0x003fc0000000000ull;
+ k->xscom_core_base = 0x10000000ull;
dc->desc = "PowerNV Chip POWER8E";
}
@@ -542,6 +543,7 @@ static void pnv_chip_power8_class_init(ObjectClass *klass,
void *data)
k->cores_mask = POWER8_CORE_MASK;
k->core_pir = pnv_chip_core_pir_p8;
k->xscom_base = 0x003fc0000000000ull;
+ k->xscom_core_base = 0x10000000ull;
dc->desc = "PowerNV Chip POWER8";
}
@@ -563,6 +565,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass
*klass, void *data)
k->cores_mask = POWER8_CORE_MASK;
k->core_pir = pnv_chip_core_pir_p8;
k->xscom_base = 0x003fc0000000000ull;
+ k->xscom_core_base = 0x10000000ull;
dc->desc = "PowerNV Chip POWER8NVL";
}
@@ -584,6 +587,7 @@ static void pnv_chip_power9_class_init(ObjectClass *klass,
void *data)
k->cores_mask = POWER9_CORE_MASK;
k->core_pir = pnv_chip_core_pir_p9;
k->xscom_base = 0x00603fc00000000ull;
+ k->xscom_core_base = 0x0ull;
dc->desc = "PowerNV Chip POWER9";
}
@@ -691,7 +695,9 @@ static void pnv_chip_realize(DeviceState *dev, Error **errp)
object_unref(OBJECT(pnv_core));
/* Each core has an XSCOM MMIO region */
- pnv_xscom_add_subregion(chip, PNV_XSCOM_EX_CORE_BASE(core_hwid),
+ pnv_xscom_add_subregion(chip,
+ PNV_XSCOM_EX_CORE_BASE(pcc->xscom_core_base,
+ core_hwid),
&PNV_CORE(pnv_core)->xscom_regs);
i++;
}
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 7bee658..df98a72 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -69,6 +69,7 @@ typedef struct PnvChipClass {
uint64_t cores_mask;
hwaddr xscom_base;
+ hwaddr xscom_core_base;
uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
} PnvChipClass;
diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
index 41a5127..0faa184 100644
--- a/include/hw/ppc/pnv_xscom.h
+++ b/include/hw/ppc/pnv_xscom.h
@@ -40,7 +40,7 @@ typedef struct PnvXScomInterfaceClass {
} PnvXScomInterfaceClass;
/*
- * Layout of the XSCOM PCB addresses of EX core 1
+ * Layout of the XSCOM PCB addresses of EX core 1 (POWER 8)
*
* GPIO 0x1100xxxx
* SCOM 0x1101xxxx
@@ -54,8 +54,7 @@ typedef struct PnvXScomInterfaceClass {
* PCB SLAVE 0x110Fxxxx
*/
-#define PNV_XSCOM_EX_BASE 0x10000000
-#define PNV_XSCOM_EX_CORE_BASE(i) (PNV_XSCOM_EX_BASE | (((uint64_t)i) << 24))
+#define PNV_XSCOM_EX_CORE_BASE(base, i) (base | (((uint64_t)i) << 24))
#define PNV_XSCOM_EX_CORE_SIZE 0x100000
#define PNV_XSCOM_LPC_BASE 0xb0020
--
2.7.4
- [Qemu-ppc] [PULL 11/19] target-ppc: Implement bcdctz. instruction, (continued)
- [Qemu-ppc] [PULL 11/19] target-ppc: Implement bcdctz. instruction, David Gibson, 2016/11/14
- [Qemu-ppc] [PULL 07/19] ppc: Remove some stub POWER6 models, David Gibson, 2016/11/14
- [Qemu-ppc] [PULL 02/19] target-ppc: add vrldnmi and vrlwmi instructions, David Gibson, 2016/11/14
- [Qemu-ppc] [PULL 05/19] powernv: CPU compatibility modes don't make sense for powernv, David Gibson, 2016/11/14
- [Qemu-ppc] [PULL 09/19] target-ppc: Implement bcdctn. instruction, David Gibson, 2016/11/14
- [Qemu-ppc] [PULL 18/19] tests: add XSCOM tests for the PowerNV machine, David Gibson, 2016/11/14
- [Qemu-ppc] [PULL 04/19] target-ppc: add vprtyb[w/d/q] instructions, David Gibson, 2016/11/14
- [Qemu-ppc] [PULL 17/19] ppc/pnv: Fix fatal bug on 32-bit hosts, David Gibson, 2016/11/14
- [Qemu-ppc] [PULL 12/19] spapr: Fix migration of PCI host bridges from qemu-2.7, David Gibson, 2016/11/14
- [Qemu-ppc] [PULL 19/19] boot-serial-test: Add a test for the powernv machine, David Gibson, 2016/11/14
- [Qemu-ppc] [PULL 15/19] ppc/pnv: add a 'xscom_core_base' field to PnvChipClass,
David Gibson <=
- [Qemu-ppc] [PULL 08/19] target-ppc: Implement bcdcfn. instruction, David Gibson, 2016/11/14
- [Qemu-ppc] [PULL 10/19] target-ppc: Implement bcdcfz. instruction, David Gibson, 2016/11/14
- Re: [Qemu-ppc] [Qemu-devel] [PULL 00/19] ppc-for-2.8 queue 20161115, Stefan Hajnoczi, 2016/11/15