qemu-ppc
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Qemu-ppc] [PATCH v6 00/10] ppc/pnv: reworking the interrupt controller


From: Cédric Le Goater
Subject: [Qemu-ppc] [PATCH v6 00/10] ppc/pnv: reworking the interrupt controller
Date: Tue, 8 Nov 2016 09:08:00 +0100

Hello,

Here is a short serie adding support for the MMIO based Interrupt
Presentation Controllers (ICP) as found on a POWER8 system. 

The initial patches are mostly cleanups and small extensions to the
XICS framework. They provide a basic container XICS object that the
PowerNV machine can use to hold the ICSs and ICPs of the system. Last
is the PSI HB model which handles the external interrupt.


The next step should be IPMI support which adds a BT device on the ISA
bus and some device tree extensions to read sensors and FRUs. This is
relatively straight forward and most of the IPMI code has been
discussed already on the list. Then should come a PHB3 model to
include some PCI devices. This is big and it needs a few helpers in
the PCI core.

If you feel adventurous, you can grab kernel and rootfs images :

  
https://openpower.xyz/job/openpower-op-build/distro=ubuntu,target=palmetto/lastSuccessfulBuild/artifact/images/zImage.epapr
  
https://openpower.xyz/job/openpower-op-build/distro=ubuntu,target=palmetto/lastSuccessfulBuild/artifact/images/rootfs.cpio.xz

and give it a try. The full patchset is available here :

   https://github.com/legoater/qemu/commits/powernv-ipmi-2.8

This is a wip branch.

Thanks,

C. 

Benjamin Herrenschmidt (3):
  ppc/pnv: Add cut down PSI bridge model and hookup external interrupt
  ppc/pnv: Add OCC model stub with interrupt support
  ppc/pnv: Add Naples chip support for LPC interrupts

Cédric Le Goater (7):
  ppc/xics: introduce a helper to insert a new ics
  ppc/xics: add a xics_get_cpu_index_by_pir helper
  ppc/xics: add a 'realize' handler to the xics_common class
  ppc/xics: add a 'set_nr_servers' handler to the xics_common class
  ppc/pnv: add a XICS object to the PowerNV machine
  ppc/pnv: add MMIO regions for ICPs
  ppc/pnv: link the CPUs to the machine XICS

 hw/intc/xics.c             |  61 +++++
 hw/intc/xics_kvm.c         |  30 +--
 hw/intc/xics_spapr.c       |  41 +---
 hw/ppc/Makefile.objs       |   2 +-
 hw/ppc/pnv.c               | 139 ++++++++++-
 hw/ppc/pnv_core.c          | 152 +++++++++++-
 hw/ppc/pnv_lpc.c           |  47 +++-
 hw/ppc/pnv_occ.c           | 136 +++++++++++
 hw/ppc/pnv_psi.c           | 574 +++++++++++++++++++++++++++++++++++++++++++++
 hw/ppc/ppc.c               |  16 ++
 include/hw/ppc/pnv.h       |  32 +++
 include/hw/ppc/pnv_core.h  |   2 +
 include/hw/ppc/pnv_lpc.h   |   9 +
 include/hw/ppc/pnv_occ.h   |  38 +++
 include/hw/ppc/pnv_psi.h   |  61 +++++
 include/hw/ppc/pnv_xscom.h |   6 +
 include/hw/ppc/xics.h      |   8 +
 target-ppc/cpu.h           |  10 +
 18 files changed, 1283 insertions(+), 81 deletions(-)
 create mode 100644 hw/ppc/pnv_occ.c
 create mode 100644 hw/ppc/pnv_psi.c
 create mode 100644 include/hw/ppc/pnv_occ.h
 create mode 100644 include/hw/ppc/pnv_psi.h

-- 
2.7.4




reply via email to

[Prev in Thread] Current Thread [Next in Thread]