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Re: [Qemu-ppc] [PATCH 3/3] ppc/pnv: add a PowerNVCPUCore object
From: |
Benjamin Herrenschmidt |
Subject: |
Re: [Qemu-ppc] [PATCH 3/3] ppc/pnv: add a PowerNVCPUCore object |
Date: |
Wed, 31 Aug 2016 11:06:53 +1000 |
On Tue, 2016-08-30 at 02:28 -0400, David Gibson wrote:
> No.. the PIR itself is a cpu level construct (and we already have a
> place for that in the cpu state). The DT id as such isn't, although
> it happens to have the same value. The fact it has the same value is
> itself a machine type property.
>
> [Aside: removing dt_id from the cpu will require disentangling it from
> the kvm vcpu id]
On P8 and P9 the PIR of a thread is a chip property, as it encodes
the HW node, chip, core and thread ID (hint: it's not 0 based on P8,
well the core isn't).
So it has to match accordingly for things like core XSCOMs which we
want to start supporting some of.
It also has to match what's in the device-tree as a pretty standard
requirement of all powerpc device-trees.
Finally it also happen to be the target interrupt server on all known
implementations.
Cheers,
Ben.
- Re: [Qemu-ppc] [PATCH 2/3] ppc/pnv: add a PnvChip object, (continued)
- [Qemu-ppc] [PATCH 3/3] ppc/pnv: add a PowerNVCPUCore object, Cédric Le Goater, 2016/08/05
- Re: [Qemu-ppc] [PATCH 3/3] ppc/pnv: add a PowerNVCPUCore object, David Gibson, 2016/08/15
- Re: [Qemu-ppc] [PATCH 3/3] ppc/pnv: add a PowerNVCPUCore object, Cédric Le Goater, 2016/08/26
- Re: [Qemu-ppc] [PATCH 3/3] ppc/pnv: add a PowerNVCPUCore object, David Gibson, 2016/08/29
- Re: [Qemu-ppc] [PATCH 3/3] ppc/pnv: add a PowerNVCPUCore object, Benjamin Herrenschmidt, 2016/08/30
- Re: [Qemu-ppc] [PATCH 3/3] ppc/pnv: add a PowerNVCPUCore object, Cédric Le Goater, 2016/08/30
- Re: [Qemu-ppc] [PATCH 3/3] ppc/pnv: add a PowerNVCPUCore object, David Gibson, 2016/08/30
- Re: [Qemu-ppc] [PATCH 3/3] ppc/pnv: add a PowerNVCPUCore object,
Benjamin Herrenschmidt <=