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Re: [Qemu-ppc] [PATCH v1 4/5] target-ppc: add vector bit permute doublew
From: |
Richard Henderson |
Subject: |
Re: [Qemu-ppc] [PATCH v1 4/5] target-ppc: add vector bit permute doubleword instruction |
Date: |
Thu, 4 Aug 2016 22:19:31 +0530 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 |
On 08/04/2016 06:33 PM, Rajalakshmi Srinivasaraghavan wrote:
+ uint64_t perm = 0;
Move the variable inside the loop.
+ VECTOR_FOR_INORDER_I(i, u64) {
+ perm = 0;
+ VECTOR_FOR_INORDER_I(j, u16) {
Surely this is more clearly written as
for (j = 0; j < 8; ++j)
since u16 really has nothing to do with this.
+ int index = VBPERMQ_INDEX(b, (i * 8) + j);
+ if (index < 64) {
+ uint64_t mask = (1ull << (63 - (index & 0x3F)));
+ if (a->u64[VBPERMQ_DW(index)] & mask) {
+ perm |= (0x80 >> j);
+ }
+ }
+ r->u64[i] = perm;
+ }
+ }
The final assignment of perm is done in the wrong loop.
r~
- [Qemu-ppc] [PATCH v1 0/5] POWER9 TCG enablement - part3, Rajalakshmi Srinivasaraghavan, 2016/08/04
- [Qemu-ppc] [PATCH v1 1/5] target-ppc: add vector insert instructions, Rajalakshmi Srinivasaraghavan, 2016/08/04
- [Qemu-ppc] [PATCH v1 2/5] target-ppc: add vector extract instructions, Rajalakshmi Srinivasaraghavan, 2016/08/04
- [Qemu-ppc] [PATCH v1 3/5] target-ppc: add vector count trailing zeros instructions, Rajalakshmi Srinivasaraghavan, 2016/08/04
- [Qemu-ppc] [PATCH v1 4/5] target-ppc: add vector bit permute doubleword instruction, Rajalakshmi Srinivasaraghavan, 2016/08/04
- Re: [Qemu-ppc] [PATCH v1 4/5] target-ppc: add vector bit permute doubleword instruction,
Richard Henderson <=
- [Qemu-ppc] [PATCH v1 5/5] target-ppc: add vector permute right indexed instruction, Rajalakshmi Srinivasaraghavan, 2016/08/04
- Re: [Qemu-ppc] [PATCH v1 0/5] POWER9 TCG enablement - part3, David Gibson, 2016/08/08