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[Qemu-ppc] [PATCH v2 5/8] target-ppc: add vcmpnez[b, h, w][.] instructio
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-ppc] [PATCH v2 5/8] target-ppc: add vcmpnez[b, h, w][.] instructions |
Date: |
Thu, 28 Jul 2016 23:44:15 +0530 |
From: Swapnil Bokade <address@hidden>
Adds following instructions:
vcmpnezb[.]: Vector Compare Not Equal or Zero Byte
vcmpnezh[.]: Vector Compare Not Equal or Zero Halfword
vcmpnezw[.]: Vector Compare Not Equal or Zero Word
Signed-off-by: Swapnil Bokade <address@hidden>
[ collapse switch case ]
Signed-off-by: Nikunj A Dadhania <address@hidden>
---
target-ppc/helper.h | 6 ++++++
target-ppc/int_helper.c | 36 ++++++++++++++++++++++++++++++++++++
target-ppc/translate/vmx-impl.c | 3 +++
target-ppc/translate/vmx-ops.c | 9 +++++++++
4 files changed, 54 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 1e68060..e6ce3ab 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -144,6 +144,9 @@ DEF_HELPER_4(vcmpequb, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpequh, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpequw, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpequd, void, env, avr, avr, avr)
+DEF_HELPER_4(vcmpnezb, void, env, avr, avr, avr)
+DEF_HELPER_4(vcmpnezh, void, env, avr, avr, avr)
+DEF_HELPER_4(vcmpnezw, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtub, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtuh, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtuw, void, env, avr, avr, avr)
@@ -160,6 +163,9 @@ DEF_HELPER_4(vcmpequb_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpequh_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpequw_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpequd_dot, void, env, avr, avr, avr)
+DEF_HELPER_4(vcmpnezb_dot, void, env, avr, avr, avr)
+DEF_HELPER_4(vcmpnezh_dot, void, env, avr, avr, avr)
+DEF_HELPER_4(vcmpnezw_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtub_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtuh_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtuw_dot, void, env, avr, avr, avr)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index ef487d0..9b4de69 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -719,6 +719,42 @@ VCMP(gtsd, >, s64)
#undef VCMP_DO
#undef VCMP
+#define VCMPNEZ_DO(suffix, element, etype, record) \
+void helper_vcmpnez##suffix(CPUPPCState *env, ppc_avr_t *r, \
+ ppc_avr_t *a, ppc_avr_t *b) \
+{ \
+ etype ones = (etype)-1; \
+ etype all = ones; \
+ etype none = 0; \
+ int i; \
+ \
+ for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
+ etype result = ((a->element[i] == 0) \
+ || (b->element[i] == 0) \
+ || (a->element[i] != b->element[i]) ? \
+ ones : 0x0); \
+ r->element[i] = result; \
+ all &= result; \
+ none |= result; \
+ } \
+ if (record) { \
+ env->crf[6] = ((all != 0) << 3) | ((none == 0) << 1); \
+ } \
+}
+
+/* VCMPNEZ - Vector compare not equal to zero
+ * suffix - instruction mnemonic suffix (b: byte, h: halfword, w: word)
+ * element - element type to access from vector
+ */
+#define VCMPNEZ(suffix, element, etype) \
+ VCMPNEZ_DO(suffix, element, etype, 0) \
+ VCMPNEZ_DO(suffix##_dot, element, etype, 1)
+VCMPNEZ(b, u8, uint8_t)
+VCMPNEZ(h, u16, uint16_t)
+VCMPNEZ(w, u32, uint32_t)
+#undef VCMPNEZ_DO
+#undef VCMPNEZ
+
#define VCMPFP_DO(suffix, compare, order, record) \
void helper_vcmp##suffix(CPUPPCState *env, ppc_avr_t *r, \
ppc_avr_t *a, ppc_avr_t *b) \
diff --git a/target-ppc/translate/vmx-impl.c b/target-ppc/translate/vmx-impl.c
index f4ee05b..da11632 100644
--- a/target-ppc/translate/vmx-impl.c
+++ b/target-ppc/translate/vmx-impl.c
@@ -477,6 +477,9 @@ GEN_VXRFORM(vcmpequb, 3, 0)
GEN_VXRFORM(vcmpequh, 3, 1)
GEN_VXRFORM(vcmpequw, 3, 2)
GEN_VXRFORM(vcmpequd, 3, 3)
+GEN_VXRFORM(vcmpnezb, 3, 4)
+GEN_VXRFORM(vcmpnezh, 3, 5)
+GEN_VXRFORM(vcmpnezw, 3, 6)
GEN_VXRFORM(vcmpgtsb, 3, 12)
GEN_VXRFORM(vcmpgtsh, 3, 13)
GEN_VXRFORM(vcmpgtsw, 3, 14)
diff --git a/target-ppc/translate/vmx-ops.c b/target-ppc/translate/vmx-ops.c
index abdef6e..137f00b 100644
--- a/target-ppc/translate/vmx-ops.c
+++ b/target-ppc/translate/vmx-ops.c
@@ -160,12 +160,21 @@ GEN_VXFORM(vminfp, 5, 17),
#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
+#define GEN_VXRFORM1_300(opname, name, str, opc2, opc3) \
+GEN_HANDLER2_E(name, str, 0x4, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA300),
#define GEN_VXRFORM(name, opc2, opc3) \
GEN_VXRFORM1(name, name, #name, opc2, opc3) \
GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
+#define GEN_VXRFORM_300(name, opc2, opc3) \
+ GEN_VXRFORM1_300(name, name, #name, opc2, opc3) \
+ GEN_VXRFORM1_300(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
+
GEN_VXRFORM(vcmpequb, 3, 0)
GEN_VXRFORM(vcmpequh, 3, 1)
GEN_VXRFORM(vcmpequw, 3, 2)
+GEN_VXRFORM_300(vcmpnezb, 3, 4)
+GEN_VXRFORM_300(vcmpnezh, 3, 5)
+GEN_VXRFORM_300(vcmpnezw, 3, 6)
GEN_VXRFORM(vcmpgtsb, 3, 12)
GEN_VXRFORM(vcmpgtsh, 3, 13)
GEN_VXRFORM(vcmpgtsw, 3, 14)
--
2.7.4
- [Qemu-ppc] [PATCH v2 0/8] POWER9 TCG enablements - part2, Nikunj A Dadhania, 2016/07/28
- [Qemu-ppc] [PATCH v2 1/8] target-ppc: implement branch-less divw[o][.], Nikunj A Dadhania, 2016/07/28
- [Qemu-ppc] [PATCH v2 2/8] target-ppc: implement branch-less divd[o][.], Nikunj A Dadhania, 2016/07/28
- [Qemu-ppc] [PATCH v2 3/8] target-ppc: add dtstsfi[q] instructions, Nikunj A Dadhania, 2016/07/28
- [Qemu-ppc] [PATCH v2 4/8] target-ppc: add vabsdu[b, h, w] instructions, Nikunj A Dadhania, 2016/07/28
- [Qemu-ppc] [PATCH v2 5/8] target-ppc: add vcmpnez[b, h, w][.] instructions,
Nikunj A Dadhania <=
- [Qemu-ppc] [PATCH v2 6/8] target-ppc: add vslv instruction, Nikunj A Dadhania, 2016/07/28
- [Qemu-ppc] [PATCH v2 7/8] target-ppc: add vsrv instruction, Nikunj A Dadhania, 2016/07/28
- [Qemu-ppc] [PATCH v2 8/8] target-ppc: add extswsli[.] instruction, Nikunj A Dadhania, 2016/07/28
- Re: [Qemu-ppc] [PATCH v2 0/8] POWER9 TCG enablements - part2, David Gibson, 2016/07/29