Re: [Qemu-ppc] [PATCH v2] ppc: Fix support for odd MSR combinations

[David Gibson]

On Mon, Jul 11, 2016 at 07:30:08PM +0100, Mark Cave-Ayland wrote:
1;4402;0c> On 11/07/16 02:55, David Gibson wrote:
> 
> > On Sat, Jul 09, 2016 at 01:41:31PM +1000, Benjamin Herrenschmidt wrote:
> >> MacOS uses an architecturally illegal MSR combination that
> >> seems nonetheless supported by 32-bit processors, which is
> >> to have MSR[PR]=1 and one or more of MSR[DR/IR/EE]=0.
> >>
> >> This adds support for it. To work properly we need to also
> >> properly include support for PR=1,{I,D}R=0 to the MMU index
> >> used by the qemu TLB.
> >>
> >> Signed-off-by: Benjamin Herrenschmidt <address@hidden>
> > 
> > Applied to ppc-for-2.7, thanks.
> 
> Hi David,
> 
> I can't see this in the ppc-for-2.7 branch on github - does it need
> a push?

Yes it did.  Done now.

-- 
David Gibson                    | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
                                | _way_ _around_!
http://www.ozlabs.org/~dgibson

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