Re: [Qemu-ppc] [PATCH] target-ppc: Multiple/String Word alignment exception

[Laurent Vivier]

On 31/03/2016 01:29, David Gibson wrote:
> On Wed, 30 Mar 2016 19:13:00 +0200
> Laurent Vivier <address@hidden> wrote:
> 
>> If the processor is in little-endian mode, an alignment interrupt must
>> occur for the following instructions: lmw, stmw, lswi, lswx, stswi or stswx.
>>
>> This is what happens with KVM, so change TCG to do the same.
>>
>> As the instruction can be emulated by the kernel, enable the change
>> only in softmmu mode.
>>
>> Signed-off-by: Laurent Vivier <address@hidden>
> 
> I guess this makes sense given the existing hardware behaviour, even
> though it seems a bit perverse to me to make the emulator strictly less
> functional.
> 
> Alex, what do you think?
> 
> Note that in time I expect we'll want some new flag to control this
> behaviour.  Given the push towards LE, I think it's pretty likely that
> future CPUs (maybe even POWER9) will allow these operations on LE
> without exceptions.
> 
> I guess one question here is what does the architecture say about
> this?  Does it say these operations will generate alignment exceptions
> on LE, or just that they may (implementation dependent)?

"Power ISA Version 2.07

Book III-S

6.5.8 Alignment Interrupt

An Alignment interrupt occurs when no higher priority
exception exists and a data access cannot be per-
formed for any of the following reasons.
...
* The instruction is lmw, stmw, lswi, lswx, stswi, or
stswx, and the operand is in storage that is Write
Through Required or Caching Inhibited, or the
thread is in Little-Endian mode.
..."

And this is very similar in

"The PowerPC Architecture,
A specification for a new family of risc processors

Book III PowerPC Operating Environment Architecture

5.5.6 Alignment Interrupt

An Alignment interrupt occurs when no higher priority
exception exists and the implementation cannot perform a storage access
for one of the reasons listed below.

...
* The instruction is lmw, stmw, lswi, lswx, stswi, or
stswx, and the processor is in Little-Endian mode.
..."

And

"Power ISA version 3.0"

Chapter 3. Fixed-Point Facility
...
lswi
...
This instruction is not supported in Little-Endian mode.
If it is executed in Little-Endian mode, the system alignment
error handler is invoked.
...
Book III

6.5.8 Alignment Interrupt
...
An Alignment interrupt occurs when no higher priority
exception exists and an attempt is made to execute an
instruction in a manner that is required, by the instruction
description, to cause an Alignment interrupt. These
cases are as follows.
„* A Load/Store Multiple instruction that is executed
in Little-Endian mode
...
An Alignment interrupt may occur when no higher priority
exception exists and a data access cannot be performed
for any of the following reasons
..."

Laurent