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[Qemu-ppc] [PULL 35/40] target-ppc: Split 44x tlbiva from ppc_tlb_invali
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 35/40] target-ppc: Split 44x tlbiva from ppc_tlb_invalidate_one() |
Date: |
Mon, 1 Feb 2016 13:31:03 +1100 |
Currently both the tlbiva instruction (used on 44x chips) and the tlbie
instruction (used on hash MMU chips) are both handled via
ppc_tlb_invalidate_one(). This is silly, because they're invoked from
different places, and do different things.
Clean this up by separating out the tlbiva instruction into its own
handling. In fact the implementation is only a stub anyway.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Laurent Vivier <address@hidden>
Acked-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: Alexander Graf <address@hidden>
---
target-ppc/helper.h | 1 +
target-ppc/mmu_helper.c | 14 ++++++++++----
target-ppc/translate.c | 2 +-
3 files changed, 12 insertions(+), 5 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 869be15..e5a8f7b 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -544,6 +544,7 @@ DEF_HELPER_2(74xx_tlbd, void, env, tl)
DEF_HELPER_2(74xx_tlbi, void, env, tl)
DEF_HELPER_FLAGS_1(tlbia, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_FLAGS_2(tlbie, TCG_CALL_NO_RWG, void, env, tl)
+DEF_HELPER_FLAGS_2(tlbiva, TCG_CALL_NO_RWG, void, env, tl)
#if defined(TARGET_PPC64)
DEF_HELPER_FLAGS_3(store_slb, TCG_CALL_NO_RWG, void, env, tl, tl)
DEF_HELPER_2(load_slb_esid, tl, env, tl)
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index 4343cb2..de4e286 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -1946,10 +1946,6 @@ void ppc_tlb_invalidate_one(CPUPPCState *env,
target_ulong addr)
ppc6xx_tlb_invalidate_virt(env, addr, 1);
}
break;
- case POWERPC_MMU_BOOKE:
- /* XXX: TODO */
- cpu_abort(CPU(cpu), "BookE MMU model is not implemented\n");
- break;
case POWERPC_MMU_32B:
case POWERPC_MMU_601:
/* tlbie invalidate TLBs for all segments */
@@ -2091,6 +2087,16 @@ void helper_tlbie(CPUPPCState *env, target_ulong addr)
ppc_tlb_invalidate_one(env, addr);
}
+void helper_tlbiva(CPUPPCState *env, target_ulong addr)
+{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
+
+ /* tlbiva instruction only exists on BookE */
+ assert(env->mmu_model == POWERPC_MMU_BOOKE);
+ /* XXX: TODO */
+ cpu_abort(CPU(cpu), "BookE MMU model is not implemented\n");
+}
+
/* Software driven TLBs management */
/* PowerPC 602/603 software TLB load instructions helpers */
static void do_6xx_tlb(CPUPPCState *env, target_ulong new_EPN, int is_code)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 3beeb45..0219d38 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -5905,7 +5905,7 @@ static void gen_tlbiva(DisasContext *ctx)
}
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
- gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
+ gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
tcg_temp_free(t0);
#endif
}
--
2.5.0
- [Qemu-ppc] [PULL 22/40] target-ppc: gdbstub: introduce avr_need_swap(), (continued)
- [Qemu-ppc] [PULL 22/40] target-ppc: gdbstub: introduce avr_need_swap(), David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 23/40] target-ppc: gdbstub: fix altivec registers for little-endian guests, David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 27/40] cuda.c: return error for unknown commands, David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 11/40] ppc: Clean up error handling in ppc_set_compat(), David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 25/40] target-ppc: gdbstub: Add VSX support, David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 24/40] target-ppc: gdbstub: fix spe registers for little-endian guests, David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 28/40] uninorth.c: add support for UniNorth kMacRISCPCIAddressSelect (0x48) register, David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 37/40] target-ppc: Helper to determine page size information from hpte alone, David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 39/40] target-ppc: Make every FPSCR_ macro have a corresponding FP_ macro, David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 31/40] target-ppc: Rework ppc_store_slb, David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 35/40] target-ppc: Split 44x tlbiva from ppc_tlb_invalidate_one(),
David Gibson <=
- [Qemu-ppc] [PULL 32/40] target-ppc: Rework SLB page size lookup, David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 30/40] target-ppc: Convert mmu-hash{32, 64}.[ch] from CPUPPCState to PowerPCCPU, David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 02/40] target-ppc: use cpu_write_xer() helper in cpu_post_load, David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 09/40] spapr: Remove abuse of rtas_ld() in h_client_architecture_support, David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 20/40] target-ppc: rename and export maybe_bswap_register(), David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 13/40] pseries: Clean up error handling in spapr_validate_node_memory(), David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 04/40] macio: add dma_active to VMStateDescription, David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 14/40] pseries: Clean up error handling in spapr_vga_init(), David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 05/40] mac_dbdma: add DBDMA controller state to VMStateDescription, David Gibson, 2016/01/31
- [Qemu-ppc] [PULL 10/40] spapr: Don't create ibm, dynamic-reconfiguration-memory w/o DR LMBs, David Gibson, 2016/01/31