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Re: [Qemu-ppc] [PATCHv2 02/10] target-ppc: Convert mmu-hash{32, 64}.[ch]
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From: |
Laurent Vivier |
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Subject: |
Re: [Qemu-ppc] [PATCHv2 02/10] target-ppc: Convert mmu-hash{32, 64}.[ch] from CPUPPCState to PowerPCCPU |
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Date: |
Wed, 27 Jan 2016 15:11:31 +0100 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.0 |
On 27/01/2016 11:13, David Gibson wrote:
> Like a lot of places these files include a mixture of functions taking
> both the older CPUPPCState *env and newer PowerPCCPU *cpu. Move a step
> closer to cleaning this up by standardizing on PowerPCCPU, except for the
> helper_* functions which are called with the CPUPPCState * from tcg.
>
> Callers and some related functions are updated as well, the boundaries of
> what's changed here are a bit arbitrary.
>
> Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Laurent Vivier <address@hidden>
> ---
> hw/ppc/spapr_hcall.c | 31 ++++++++++---------
> target-ppc/kvm.c | 2 +-
> target-ppc/mmu-hash32.c | 68 +++++++++++++++++++++++------------------
> target-ppc/mmu-hash32.h | 30 ++++++++++---------
> target-ppc/mmu-hash64.c | 80
> +++++++++++++++++++++++++++++--------------------
> target-ppc/mmu-hash64.h | 21 ++++++-------
> target-ppc/mmu_helper.c | 13 ++++----
> 7 files changed, 136 insertions(+), 109 deletions(-)
>
> diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
> index c4ae255..4707196 100644
> --- a/hw/ppc/spapr_hcall.c
> +++ b/hw/ppc/spapr_hcall.c
> @@ -160,7 +160,7 @@ static target_ulong h_enter(PowerPCCPU *cpu,
> sPAPRMachineState *spapr,
> pte_index &= ~7ULL;
> token = ppc_hash64_start_access(cpu, pte_index);
> for (; index < 8; index++) {
> - if ((ppc_hash64_load_hpte0(env, token, index) & HPTE64_V_VALID)
> == 0) {
> + if (!(ppc_hash64_load_hpte0(cpu, token, index) &
> HPTE64_V_VALID)) {
> break;
> }
> }
> @@ -170,14 +170,14 @@ static target_ulong h_enter(PowerPCCPU *cpu,
> sPAPRMachineState *spapr,
> }
> } else {
> token = ppc_hash64_start_access(cpu, pte_index);
> - if (ppc_hash64_load_hpte0(env, token, 0) & HPTE64_V_VALID) {
> + if (ppc_hash64_load_hpte0(cpu, token, 0) & HPTE64_V_VALID) {
> ppc_hash64_stop_access(token);
> return H_PTEG_FULL;
> }
> ppc_hash64_stop_access(token);
> }
>
> - ppc_hash64_store_hpte(env, pte_index + index,
> + ppc_hash64_store_hpte(cpu, pte_index + index,
> pteh | HPTE64_V_HPTE_DIRTY, ptel);
>
> args[0] = pte_index + index;
> @@ -191,11 +191,12 @@ typedef enum {
> REMOVE_HW = 3,
> } RemoveResult;
>
> -static RemoveResult remove_hpte(CPUPPCState *env, target_ulong ptex,
> +static RemoveResult remove_hpte(PowerPCCPU *cpu, target_ulong ptex,
> target_ulong avpn,
> target_ulong flags,
> target_ulong *vp, target_ulong *rp)
> {
> + CPUPPCState *env = &cpu->env;
> uint64_t token;
> target_ulong v, r, rb;
>
> @@ -203,9 +204,9 @@ static RemoveResult remove_hpte(CPUPPCState *env,
> target_ulong ptex,
> return REMOVE_PARM;
> }
>
> - token = ppc_hash64_start_access(ppc_env_get_cpu(env), ptex);
> - v = ppc_hash64_load_hpte0(env, token, 0);
> - r = ppc_hash64_load_hpte1(env, token, 0);
> + token = ppc_hash64_start_access(cpu, ptex);
> + v = ppc_hash64_load_hpte0(cpu, token, 0);
> + r = ppc_hash64_load_hpte1(cpu, token, 0);
> ppc_hash64_stop_access(token);
>
> if ((v & HPTE64_V_VALID) == 0 ||
> @@ -215,7 +216,7 @@ static RemoveResult remove_hpte(CPUPPCState *env,
> target_ulong ptex,
> }
> *vp = v;
> *rp = r;
> - ppc_hash64_store_hpte(env, ptex, HPTE64_V_HPTE_DIRTY, 0);
> + ppc_hash64_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0);
> rb = compute_tlbie_rb(v, r, ptex);
> ppc_tlb_invalidate_one(env, rb);
> return REMOVE_SUCCESS;
> @@ -224,13 +225,12 @@ static RemoveResult remove_hpte(CPUPPCState *env,
> target_ulong ptex,
> static target_ulong h_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> target_ulong opcode, target_ulong *args)
> {
> - CPUPPCState *env = &cpu->env;
> target_ulong flags = args[0];
> target_ulong pte_index = args[1];
> target_ulong avpn = args[2];
> RemoveResult ret;
>
> - ret = remove_hpte(env, pte_index, avpn, flags,
> + ret = remove_hpte(cpu, pte_index, avpn, flags,
> &args[0], &args[1]);
>
> switch (ret) {
> @@ -271,7 +271,6 @@ static target_ulong h_remove(PowerPCCPU *cpu,
> sPAPRMachineState *spapr,
> static target_ulong h_bulk_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> target_ulong opcode, target_ulong *args)
> {
> - CPUPPCState *env = &cpu->env;
> int i;
>
> for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) {
> @@ -293,7 +292,7 @@ static target_ulong h_bulk_remove(PowerPCCPU *cpu,
> sPAPRMachineState *spapr,
> return H_PARAMETER;
> }
>
> - ret = remove_hpte(env, *tsh & H_BULK_REMOVE_PTEX, tsl,
> + ret = remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl,
> (*tsh & H_BULK_REMOVE_FLAGS) >> 26,
> &v, &r);
>
> @@ -330,8 +329,8 @@ static target_ulong h_protect(PowerPCCPU *cpu,
> sPAPRMachineState *spapr,
> }
>
> token = ppc_hash64_start_access(cpu, pte_index);
> - v = ppc_hash64_load_hpte0(env, token, 0);
> - r = ppc_hash64_load_hpte1(env, token, 0);
> + v = ppc_hash64_load_hpte0(cpu, token, 0);
> + r = ppc_hash64_load_hpte1(cpu, token, 0);
> ppc_hash64_stop_access(token);
>
> if ((v & HPTE64_V_VALID) == 0 ||
> @@ -345,11 +344,11 @@ static target_ulong h_protect(PowerPCCPU *cpu,
> sPAPRMachineState *spapr,
> r |= (flags << 48) & HPTE64_R_KEY_HI;
> r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO);
> rb = compute_tlbie_rb(v, r, pte_index);
> - ppc_hash64_store_hpte(env, pte_index,
> + ppc_hash64_store_hpte(cpu, pte_index,
> (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0);
> ppc_tlb_invalidate_one(env, rb);
> /* Don't need a memory barrier, due to qemu's global lock */
> - ppc_hash64_store_hpte(env, pte_index, v | HPTE64_V_HPTE_DIRTY, r);
> + ppc_hash64_store_hpte(cpu, pte_index, v | HPTE64_V_HPTE_DIRTY, r);
> return H_SUCCESS;
> }
>
> diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
> index 4524999..98d7ba6 100644
> --- a/target-ppc/kvm.c
> +++ b/target-ppc/kvm.c
> @@ -1205,7 +1205,7 @@ int kvm_arch_get_registers(CPUState *cs)
> * Only restore valid entries
> */
> if (rb & SLB_ESID_V) {
> - ppc_store_slb(env, rb, rs);
> + ppc_store_slb(cpu, rb, rs);
> }
> }
> #endif
> diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c
> index a00ae3c..4497480 100644
> --- a/target-ppc/mmu-hash32.c
> +++ b/target-ppc/mmu-hash32.c
> @@ -83,9 +83,10 @@ static int ppc_hash32_pp_prot(int key, int pp, int nx)
> return prot;
> }
>
> -static int ppc_hash32_pte_prot(CPUPPCState *env,
> +static int ppc_hash32_pte_prot(PowerPCCPU *cpu,
> target_ulong sr, ppc_hash_pte32_t pte)
> {
> + CPUPPCState *env = &cpu->env;
> unsigned pp, key;
>
> key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));
> @@ -94,9 +95,11 @@ static int ppc_hash32_pte_prot(CPUPPCState *env,
> return ppc_hash32_pp_prot(key, pp, !!(sr & SR32_NX));
> }
>
> -static target_ulong hash32_bat_size(CPUPPCState *env,
> +static target_ulong hash32_bat_size(PowerPCCPU *cpu,
> target_ulong batu, target_ulong batl)
> {
> + CPUPPCState *env = &cpu->env;
> +
> if ((msr_pr && !(batu & BATU32_VP))
> || (!msr_pr && !(batu & BATU32_VS))) {
> return 0;
> @@ -105,7 +108,7 @@ static target_ulong hash32_bat_size(CPUPPCState *env,
> return BATU32_BEPI & ~((batu & BATU32_BL) << 15);
> }
>
> -static int hash32_bat_prot(CPUPPCState *env,
> +static int hash32_bat_prot(PowerPCCPU *cpu,
> target_ulong batu, target_ulong batl)
> {
> int pp, prot;
> @@ -121,7 +124,7 @@ static int hash32_bat_prot(CPUPPCState *env,
> return prot;
> }
>
> -static target_ulong hash32_bat_601_size(CPUPPCState *env,
> +static target_ulong hash32_bat_601_size(PowerPCCPU *cpu,
> target_ulong batu, target_ulong batl)
> {
> if (!(batl & BATL32_601_V)) {
> @@ -131,9 +134,10 @@ static target_ulong hash32_bat_601_size(CPUPPCState *env,
> return BATU32_BEPI & ~((batl & BATL32_601_BL) << 17);
> }
>
> -static int hash32_bat_601_prot(CPUPPCState *env,
> +static int hash32_bat_601_prot(PowerPCCPU *cpu,
> target_ulong batu, target_ulong batl)
> {
> + CPUPPCState *env = &cpu->env;
> int key, pp;
>
> pp = batu & BATU32_601_PP;
> @@ -145,9 +149,10 @@ static int hash32_bat_601_prot(CPUPPCState *env,
> return ppc_hash32_pp_prot(key, pp, 0);
> }
>
> -static hwaddr ppc_hash32_bat_lookup(CPUPPCState *env, target_ulong ea, int
> rwx,
> +static hwaddr ppc_hash32_bat_lookup(PowerPCCPU *cpu, target_ulong ea, int
> rwx,
> int *prot)
> {
> + CPUPPCState *env = &cpu->env;
> target_ulong *BATlt, *BATut;
> int i;
>
> @@ -166,9 +171,9 @@ static hwaddr ppc_hash32_bat_lookup(CPUPPCState *env,
> target_ulong ea, int rwx,
> target_ulong mask;
>
> if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
> - mask = hash32_bat_601_size(env, batu, batl);
> + mask = hash32_bat_601_size(cpu, batu, batl);
> } else {
> - mask = hash32_bat_size(env, batu, batl);
> + mask = hash32_bat_size(cpu, batu, batl);
> }
> LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
> " BATl " TARGET_FMT_lx "\n", __func__,
> @@ -178,9 +183,9 @@ static hwaddr ppc_hash32_bat_lookup(CPUPPCState *env,
> target_ulong ea, int rwx,
> hwaddr raddr = (batl & mask) | (ea & ~mask);
>
> if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
> - *prot = hash32_bat_601_prot(env, batu, batl);
> + *prot = hash32_bat_601_prot(cpu, batu, batl);
> } else {
> - *prot = hash32_bat_prot(env, batu, batl);
> + *prot = hash32_bat_prot(cpu, batu, batl);
> }
>
> return raddr & TARGET_PAGE_MASK;
> @@ -209,11 +214,12 @@ static hwaddr ppc_hash32_bat_lookup(CPUPPCState *env,
> target_ulong ea, int rwx,
> return -1;
> }
>
> -static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr,
> +static int ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr,
> target_ulong eaddr, int rwx,
> hwaddr *raddr, int *prot)
> {
> - CPUState *cs = CPU(ppc_env_get_cpu(env));
> + CPUState *cs = CPU(cpu);
> + CPUPPCState *env = &cpu->env;
> int key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));
>
> qemu_log_mask(CPU_LOG_MMU, "direct store...\n");
> @@ -293,12 +299,14 @@ static int ppc_hash32_direct_store(CPUPPCState *env,
> target_ulong sr,
> }
> }
>
> -hwaddr get_pteg_offset32(CPUPPCState *env, hwaddr hash)
> +hwaddr get_pteg_offset32(PowerPCCPU *cpu, hwaddr hash)
> {
> + CPUPPCState *env = &cpu->env;
> +
> return (hash * HASH_PTEG_SIZE_32) & env->htab_mask;
> }
>
> -static hwaddr ppc_hash32_pteg_search(CPUPPCState *env, hwaddr pteg_off,
> +static hwaddr ppc_hash32_pteg_search(PowerPCCPU *cpu, hwaddr pteg_off,
> bool secondary, target_ulong ptem,
> ppc_hash_pte32_t *pte)
> {
> @@ -307,8 +315,8 @@ static hwaddr ppc_hash32_pteg_search(CPUPPCState *env,
> hwaddr pteg_off,
> int i;
>
> for (i = 0; i < HPTES_PER_GROUP; i++) {
> - pte0 = ppc_hash32_load_hpte0(env, pte_offset);
> - pte1 = ppc_hash32_load_hpte1(env, pte_offset);
> + pte0 = ppc_hash32_load_hpte0(cpu, pte_offset);
> + pte1 = ppc_hash32_load_hpte1(cpu, pte_offset);
>
> if ((pte0 & HPTE32_V_VALID)
> && (secondary == !!(pte0 & HPTE32_V_SECONDARY))
> @@ -324,10 +332,11 @@ static hwaddr ppc_hash32_pteg_search(CPUPPCState *env,
> hwaddr pteg_off,
> return -1;
> }
>
> -static hwaddr ppc_hash32_htab_lookup(CPUPPCState *env,
> +static hwaddr ppc_hash32_htab_lookup(PowerPCCPU *cpu,
> target_ulong sr, target_ulong eaddr,
> ppc_hash_pte32_t *pte)
> {
> + CPUPPCState *env = &cpu->env;
> hwaddr pteg_off, pte_offset;
> hwaddr hash;
> uint32_t vsid, pgidx, ptem;
> @@ -348,16 +357,16 @@ static hwaddr ppc_hash32_htab_lookup(CPUPPCState *env,
> " vsid=%" PRIx32 " ptem=%" PRIx32
> " hash=" TARGET_FMT_plx "\n",
> env->htab_base, env->htab_mask, vsid, ptem, hash);
> - pteg_off = get_pteg_offset32(env, hash);
> - pte_offset = ppc_hash32_pteg_search(env, pteg_off, 0, ptem, pte);
> + pteg_off = get_pteg_offset32(cpu, hash);
> + pte_offset = ppc_hash32_pteg_search(cpu, pteg_off, 0, ptem, pte);
> if (pte_offset == -1) {
> /* Secondary PTEG lookup */
> qemu_log_mask(CPU_LOG_MMU, "1 htab=" TARGET_FMT_plx "/"
> TARGET_FMT_plx
> " vsid=%" PRIx32 " api=%" PRIx32
> " hash=" TARGET_FMT_plx "\n", env->htab_base,
> env->htab_mask, vsid, ptem, ~hash);
> - pteg_off = get_pteg_offset32(env, ~hash);
> - pte_offset = ppc_hash32_pteg_search(env, pteg_off, 1, ptem, pte);
> + pteg_off = get_pteg_offset32(cpu, ~hash);
> + pte_offset = ppc_hash32_pteg_search(cpu, pteg_off, 1, ptem, pte);
> }
>
> return pte_offset;
> @@ -399,7 +408,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu,
> target_ulong eaddr, int rwx,
>
> /* 2. Check Block Address Translation entries (BATs) */
> if (env->nb_BATs != 0) {
> - raddr = ppc_hash32_bat_lookup(env, eaddr, rwx, &prot);
> + raddr = ppc_hash32_bat_lookup(cpu, eaddr, rwx, &prot);
> if (raddr != -1) {
> if (need_prot[rwx] & ~prot) {
> if (rwx == 2) {
> @@ -430,7 +439,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu,
> target_ulong eaddr, int rwx,
>
> /* 4. Handle direct store segments */
> if (sr & SR32_T) {
> - if (ppc_hash32_direct_store(env, sr, eaddr, rwx,
> + if (ppc_hash32_direct_store(cpu, sr, eaddr, rwx,
> &raddr, &prot) == 0) {
> tlb_set_page(cs, eaddr & TARGET_PAGE_MASK,
> raddr & TARGET_PAGE_MASK, prot, mmu_idx,
> @@ -449,7 +458,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu,
> target_ulong eaddr, int rwx,
> }
>
> /* 6. Locate the PTE in the hash table */
> - pte_offset = ppc_hash32_htab_lookup(env, sr, eaddr, &pte);
> + pte_offset = ppc_hash32_htab_lookup(cpu, sr, eaddr, &pte);
> if (pte_offset == -1) {
> if (rwx == 2) {
> cs->exception_index = POWERPC_EXCP_ISI;
> @@ -472,7 +481,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu,
> target_ulong eaddr, int rwx,
>
> /* 7. Check access permissions */
>
> - prot = ppc_hash32_pte_prot(env, sr, pte);
> + prot = ppc_hash32_pte_prot(cpu, sr, pte);
>
> if (need_prot[rwx] & ~prot) {
> /* Access right violation */
> @@ -507,7 +516,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu,
> target_ulong eaddr, int rwx,
> }
>
> if (new_pte1 != pte.pte1) {
> - ppc_hash32_store_hpte1(env, pte_offset, new_pte1);
> + ppc_hash32_store_hpte1(cpu, pte_offset, new_pte1);
> }
>
> /* 9. Determine the real address from the PTE */
> @@ -520,8 +529,9 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu,
> target_ulong eaddr, int rwx,
> return 0;
> }
>
> -hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env, target_ulong eaddr)
> +hwaddr ppc_hash32_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr)
> {
> + CPUPPCState *env = &cpu->env;
> target_ulong sr;
> hwaddr pte_offset;
> ppc_hash_pte32_t pte;
> @@ -533,7 +543,7 @@ hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env,
> target_ulong eaddr)
> }
>
> if (env->nb_BATs != 0) {
> - hwaddr raddr = ppc_hash32_bat_lookup(env, eaddr, 0, &prot);
> + hwaddr raddr = ppc_hash32_bat_lookup(cpu, eaddr, 0, &prot);
> if (raddr != -1) {
> return raddr;
> }
> @@ -546,7 +556,7 @@ hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env,
> target_ulong eaddr)
> return -1;
> }
>
> - pte_offset = ppc_hash32_htab_lookup(env, sr, eaddr, &pte);
> + pte_offset = ppc_hash32_htab_lookup(cpu, sr, eaddr, &pte);
> if (pte_offset == -1) {
> return -1;
> }
> diff --git a/target-ppc/mmu-hash32.h b/target-ppc/mmu-hash32.h
> index d515d4f..afbb9dd 100644
> --- a/target-ppc/mmu-hash32.h
> +++ b/target-ppc/mmu-hash32.h
> @@ -3,8 +3,8 @@
>
> #ifndef CONFIG_USER_ONLY
>
> -hwaddr get_pteg_offset32(CPUPPCState *env, hwaddr hash);
> -hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env, target_ulong addr);
> +hwaddr get_pteg_offset32(PowerPCCPU *cpu, hwaddr hash);
> +hwaddr ppc_hash32_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr);
> int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong address, int
> rw,
> int mmu_idx);
>
> @@ -65,40 +65,42 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu,
> target_ulong address, int rw,
> #define HPTE32_R_WIMG 0x00000078
> #define HPTE32_R_PP 0x00000003
>
> -static inline target_ulong ppc_hash32_load_hpte0(CPUPPCState *env,
> +static inline target_ulong ppc_hash32_load_hpte0(PowerPCCPU *cpu,
> hwaddr pte_offset)
> {
> - CPUState *cs = CPU(ppc_env_get_cpu(env));
> + CPUPPCState *env = &cpu->env;
>
> assert(!env->external_htab); /* Not supported on 32-bit for now */
> - return ldl_phys(cs->as, env->htab_base + pte_offset);
> + return ldl_phys(CPU(cpu)->as, env->htab_base + pte_offset);
> }
>
> -static inline target_ulong ppc_hash32_load_hpte1(CPUPPCState *env,
> +static inline target_ulong ppc_hash32_load_hpte1(PowerPCCPU *cpu,
> hwaddr pte_offset)
> {
> - CPUState *cs = CPU(ppc_env_get_cpu(env));
> + CPUPPCState *env = &cpu->env;
>
> assert(!env->external_htab); /* Not supported on 32-bit for now */
> - return ldl_phys(cs->as, env->htab_base + pte_offset +
> HASH_PTE_SIZE_32/2);
> + return ldl_phys(CPU(cpu)->as,
> + env->htab_base + pte_offset + HASH_PTE_SIZE_32 / 2);
> }
>
> -static inline void ppc_hash32_store_hpte0(CPUPPCState *env,
> +static inline void ppc_hash32_store_hpte0(PowerPCCPU *cpu,
> hwaddr pte_offset, target_ulong
> pte0)
> {
> - CPUState *cs = CPU(ppc_env_get_cpu(env));
> + CPUPPCState *env = &cpu->env;
>
> assert(!env->external_htab); /* Not supported on 32-bit for now */
> - stl_phys(cs->as, env->htab_base + pte_offset, pte0);
> + stl_phys(CPU(cpu)->as, env->htab_base + pte_offset, pte0);
> }
>
> -static inline void ppc_hash32_store_hpte1(CPUPPCState *env,
> +static inline void ppc_hash32_store_hpte1(PowerPCCPU *cpu,
> hwaddr pte_offset, target_ulong
> pte1)
> {
> - CPUState *cs = CPU(ppc_env_get_cpu(env));
> + CPUPPCState *env = &cpu->env;
>
> assert(!env->external_htab); /* Not supported on 32-bit for now */
> - stl_phys(cs->as, env->htab_base + pte_offset + HASH_PTE_SIZE_32/2, pte1);
> + stl_phys(CPU(cpu)->as,
> + env->htab_base + pte_offset + HASH_PTE_SIZE_32 / 2, pte1);
> }
>
> typedef struct {
> diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
> index 34e20fa..03e25fd 100644
> --- a/target-ppc/mmu-hash64.c
> +++ b/target-ppc/mmu-hash64.c
> @@ -40,8 +40,9 @@ bool kvmppc_kern_htab;
> * SLB handling
> */
>
> -static ppc_slb_t *slb_lookup(CPUPPCState *env, target_ulong eaddr)
> +static ppc_slb_t *slb_lookup(PowerPCCPU *cpu, target_ulong eaddr)
> {
> + CPUPPCState *env = &cpu->env;
> uint64_t esid_256M, esid_1T;
> int n;
>
> @@ -69,12 +70,13 @@ static ppc_slb_t *slb_lookup(CPUPPCState *env,
> target_ulong eaddr)
> return NULL;
> }
>
> -void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
> +void dump_slb(FILE *f, fprintf_function cpu_fprintf, PowerPCCPU *cpu)
> {
> + CPUPPCState *env = &cpu->env;
> int i;
> uint64_t slbe, slbv;
>
> - cpu_synchronize_state(CPU(ppc_env_get_cpu(env)));
> + cpu_synchronize_state(CPU(cpu));
>
> cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n");
> for (i = 0; i < env->slb_nr; i++) {
> @@ -117,7 +119,7 @@ void helper_slbie(CPUPPCState *env, target_ulong addr)
> PowerPCCPU *cpu = ppc_env_get_cpu(env);
> ppc_slb_t *slb;
>
> - slb = slb_lookup(env, addr);
> + slb = slb_lookup(cpu, addr);
> if (!slb) {
> return;
> }
> @@ -133,8 +135,9 @@ void helper_slbie(CPUPPCState *env, target_ulong addr)
> }
> }
>
> -int ppc_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
> +int ppc_store_slb(PowerPCCPU *cpu, target_ulong rb, target_ulong rs)
> {
> + CPUPPCState *env = &cpu->env;
> int slot = rb & 0xfff;
> ppc_slb_t *slb = &env->slb[slot];
>
> @@ -159,9 +162,10 @@ int ppc_store_slb(CPUPPCState *env, target_ulong rb,
> target_ulong rs)
> return 0;
> }
>
> -static int ppc_load_slb_esid(CPUPPCState *env, target_ulong rb,
> +static int ppc_load_slb_esid(PowerPCCPU *cpu, target_ulong rb,
> target_ulong *rt)
> {
> + CPUPPCState *env = &cpu->env;
> int slot = rb & 0xfff;
> ppc_slb_t *slb = &env->slb[slot];
>
> @@ -173,9 +177,10 @@ static int ppc_load_slb_esid(CPUPPCState *env,
> target_ulong rb,
> return 0;
> }
>
> -static int ppc_load_slb_vsid(CPUPPCState *env, target_ulong rb,
> +static int ppc_load_slb_vsid(PowerPCCPU *cpu, target_ulong rb,
> target_ulong *rt)
> {
> + CPUPPCState *env = &cpu->env;
> int slot = rb & 0xfff;
> ppc_slb_t *slb = &env->slb[slot];
>
> @@ -189,7 +194,9 @@ static int ppc_load_slb_vsid(CPUPPCState *env,
> target_ulong rb,
>
> void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
> {
> - if (ppc_store_slb(env, rb, rs) < 0) {
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> +
> + if (ppc_store_slb(cpu, rb, rs) < 0) {
> helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
> POWERPC_EXCP_INVAL);
> }
> @@ -197,9 +204,10 @@ void helper_store_slb(CPUPPCState *env, target_ulong rb,
> target_ulong rs)
>
> target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)
> {
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> target_ulong rt = 0;
>
> - if (ppc_load_slb_esid(env, rb, &rt) < 0) {
> + if (ppc_load_slb_esid(cpu, rb, &rt) < 0) {
> helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
> POWERPC_EXCP_INVAL);
> }
> @@ -208,9 +216,10 @@ target_ulong helper_load_slb_esid(CPUPPCState *env,
> target_ulong rb)
>
> target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
> {
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> target_ulong rt = 0;
>
> - if (ppc_load_slb_vsid(env, rb, &rt) < 0) {
> + if (ppc_load_slb_vsid(cpu, rb, &rt) < 0) {
> helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
> POWERPC_EXCP_INVAL);
> }
> @@ -221,9 +230,10 @@ target_ulong helper_load_slb_vsid(CPUPPCState *env,
> target_ulong rb)
> * 64-bit hash table MMU handling
> */
>
> -static int ppc_hash64_pte_prot(CPUPPCState *env,
> +static int ppc_hash64_pte_prot(PowerPCCPU *cpu,
> ppc_slb_t *slb, ppc_hash_pte64_t pte)
> {
> + CPUPPCState *env = &cpu->env;
> unsigned pp, key;
> /* Some pp bit combinations have undefined behaviour, so default
> * to no access in those cases */
> @@ -273,12 +283,12 @@ static int ppc_hash64_pte_prot(CPUPPCState *env,
> return prot;
> }
>
> -static int ppc_hash64_amr_prot(CPUPPCState *env, ppc_hash_pte64_t pte)
> +static int ppc_hash64_amr_prot(PowerPCCPU *cpu, ppc_hash_pte64_t pte)
> {
> + CPUPPCState *env = &cpu->env;
> int key, amrbits;
> int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
>
> -
> /* Only recent MMUs implement Virtual Page Class Key Protection */
> if (!(env->mmu_model & POWERPC_MMU_AMR)) {
> return prot;
> @@ -347,23 +357,24 @@ void ppc_hash64_stop_access(uint64_t token)
> }
> }
>
> -static hwaddr ppc_hash64_pteg_search(CPUPPCState *env, hwaddr hash,
> +static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash,
> bool secondary, target_ulong ptem,
> ppc_hash_pte64_t *pte)
> {
> + CPUPPCState *env = &cpu->env;
> int i;
> uint64_t token;
> target_ulong pte0, pte1;
> target_ulong pte_index;
>
> pte_index = (hash & env->htab_mask) * HPTES_PER_GROUP;
> - token = ppc_hash64_start_access(ppc_env_get_cpu(env), pte_index);
> + token = ppc_hash64_start_access(cpu, pte_index);
> if (!token) {
> return -1;
> }
> for (i = 0; i < HPTES_PER_GROUP; i++) {
> - pte0 = ppc_hash64_load_hpte0(env, token, i);
> - pte1 = ppc_hash64_load_hpte1(env, token, i);
> + pte0 = ppc_hash64_load_hpte0(cpu, token, i);
> + pte1 = ppc_hash64_load_hpte1(cpu, token, i);
>
> if ((pte0 & HPTE64_V_VALID)
> && (secondary == !!(pte0 & HPTE64_V_SECONDARY))
> @@ -399,10 +410,11 @@ static uint64_t ppc_hash64_page_shift(ppc_slb_t *slb)
> return epnshift;
> }
>
> -static hwaddr ppc_hash64_htab_lookup(CPUPPCState *env,
> +static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
> ppc_slb_t *slb, target_ulong eaddr,
> ppc_hash_pte64_t *pte)
> {
> + CPUPPCState *env = &cpu->env;
> hwaddr pte_offset;
> hwaddr hash;
> uint64_t vsid, epnshift, epnmask, epn, ptem;
> @@ -435,7 +447,7 @@ static hwaddr ppc_hash64_htab_lookup(CPUPPCState *env,
> " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
> " hash=" TARGET_FMT_plx "\n",
> env->htab_base, env->htab_mask, vsid, ptem, hash);
> - pte_offset = ppc_hash64_pteg_search(env, hash, 0, ptem, pte);
> + pte_offset = ppc_hash64_pteg_search(cpu, hash, 0, ptem, pte);
>
> if (pte_offset == -1) {
> /* Secondary PTEG lookup */
> @@ -445,7 +457,7 @@ static hwaddr ppc_hash64_htab_lookup(CPUPPCState *env,
> " hash=" TARGET_FMT_plx "\n", env->htab_base,
> env->htab_mask, vsid, ptem, ~hash);
>
> - pte_offset = ppc_hash64_pteg_search(env, ~hash, 1, ptem, pte);
> + pte_offset = ppc_hash64_pteg_search(cpu, ~hash, 1, ptem, pte);
> }
>
> return pte_offset;
> @@ -492,7 +504,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu,
> target_ulong eaddr,
> }
>
> /* 2. Translation is on, so look up the SLB */
> - slb = slb_lookup(env, eaddr);
> + slb = slb_lookup(cpu, eaddr);
>
> if (!slb) {
> if (rwx == 2) {
> @@ -514,7 +526,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu,
> target_ulong eaddr,
> }
>
> /* 4. Locate the PTE in the hash table */
> - pte_offset = ppc_hash64_htab_lookup(env, slb, eaddr, &pte);
> + pte_offset = ppc_hash64_htab_lookup(cpu, slb, eaddr, &pte);
> if (pte_offset == -1) {
> if (rwx == 2) {
> cs->exception_index = POWERPC_EXCP_ISI;
> @@ -536,8 +548,8 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu,
> target_ulong eaddr,
>
> /* 5. Check access permissions */
>
> - pp_prot = ppc_hash64_pte_prot(env, slb, pte);
> - amr_prot = ppc_hash64_amr_prot(env, pte);
> + pp_prot = ppc_hash64_pte_prot(cpu, slb, pte);
> + amr_prot = ppc_hash64_amr_prot(cpu, pte);
> prot = pp_prot & amr_prot;
>
> if ((need_prot[rwx] & ~prot) != 0) {
> @@ -580,7 +592,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu,
> target_ulong eaddr,
> }
>
> if (new_pte1 != pte.pte1) {
> - ppc_hash64_store_hpte(env, pte_offset / HASH_PTE_SIZE_64,
> + ppc_hash64_store_hpte(cpu, pte_offset / HASH_PTE_SIZE_64,
> pte.pte0, new_pte1);
> }
>
> @@ -594,8 +606,9 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu,
> target_ulong eaddr,
> return 0;
> }
>
> -hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env, target_ulong addr)
> +hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr)
> {
> + CPUPPCState *env = &cpu->env;
> ppc_slb_t *slb;
> hwaddr pte_offset;
> ppc_hash_pte64_t pte;
> @@ -605,12 +618,12 @@ hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env,
> target_ulong addr)
> return addr & 0x0FFFFFFFFFFFFFFFULL;
> }
>
> - slb = slb_lookup(env, addr);
> + slb = slb_lookup(cpu, addr);
> if (!slb) {
> return -1;
> }
>
> - pte_offset = ppc_hash64_htab_lookup(env, slb, addr, &pte);
> + pte_offset = ppc_hash64_htab_lookup(cpu, slb, addr, &pte);
> if (pte_offset == -1) {
> return -1;
> }
> @@ -618,11 +631,11 @@ hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env,
> target_ulong addr)
> return ppc_hash64_pte_raddr(slb, pte, addr) & TARGET_PAGE_MASK;
> }
>
> -void ppc_hash64_store_hpte(CPUPPCState *env,
> +void ppc_hash64_store_hpte(PowerPCCPU *cpu,
> target_ulong pte_index,
> target_ulong pte0, target_ulong pte1)
> {
> - CPUState *cs = CPU(ppc_env_get_cpu(env));
> + CPUPPCState *env = &cpu->env;
>
> if (kvmppc_kern_htab) {
> kvmppc_hash64_write_pte(env, pte_index, pte0, pte1);
> @@ -632,9 +645,10 @@ void ppc_hash64_store_hpte(CPUPPCState *env,
> pte_index *= HASH_PTE_SIZE_64;
> if (env->external_htab) {
> stq_p(env->external_htab + pte_index, pte0);
> - stq_p(env->external_htab + pte_index + HASH_PTE_SIZE_64/2, pte1);
> + stq_p(env->external_htab + pte_index + HASH_PTE_SIZE_64 / 2, pte1);
> } else {
> - stq_phys(cs->as, env->htab_base + pte_index, pte0);
> - stq_phys(cs->as, env->htab_base + pte_index + HASH_PTE_SIZE_64/2,
> pte1);
> + stq_phys(CPU(cpu)->as, env->htab_base + pte_index, pte0);
> + stq_phys(CPU(cpu)->as,
> + env->htab_base + pte_index + HASH_PTE_SIZE_64 / 2, pte1);
> }
> }
> diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h
> index 291750f..6e3de7e 100644
> --- a/target-ppc/mmu-hash64.h
> +++ b/target-ppc/mmu-hash64.h
> @@ -4,12 +4,13 @@
> #ifndef CONFIG_USER_ONLY
>
> #ifdef TARGET_PPC64
> -void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
> -int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs);
> -hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env, target_ulong addr);
> +void ppc_hash64_check_page_sizes(PowerPCCPU *cpu, Error **errp);
> +void dump_slb(FILE *f, fprintf_function cpu_fprintf, PowerPCCPU *cpu);
> +int ppc_store_slb(PowerPCCPU *cpu, target_ulong rb, target_ulong rs);
> +hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr);
> int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong address, int
> rw,
> int mmu_idx);
> -void ppc_hash64_store_hpte(CPUPPCState *env, target_ulong index,
> +void ppc_hash64_store_hpte(PowerPCCPU *cpu, target_ulong index,
> target_ulong pte0, target_ulong pte1);
> #endif
>
> @@ -85,31 +86,31 @@ extern bool kvmppc_kern_htab;
> uint64_t ppc_hash64_start_access(PowerPCCPU *cpu, target_ulong pte_index);
> void ppc_hash64_stop_access(uint64_t token);
>
> -static inline target_ulong ppc_hash64_load_hpte0(CPUPPCState *env,
> +static inline target_ulong ppc_hash64_load_hpte0(PowerPCCPU *cpu,
> uint64_t token, int index)
> {
> - CPUState *cs = CPU(ppc_env_get_cpu(env));
> + CPUPPCState *env = &cpu->env;
> uint64_t addr;
>
> addr = token + (index * HASH_PTE_SIZE_64);
> if (env->external_htab) {
> return ldq_p((const void *)(uintptr_t)addr);
> } else {
> - return ldq_phys(cs->as, addr);
> + return ldq_phys(CPU(cpu)->as, addr);
> }
> }
>
> -static inline target_ulong ppc_hash64_load_hpte1(CPUPPCState *env,
> +static inline target_ulong ppc_hash64_load_hpte1(PowerPCCPU *cpu,
> uint64_t token, int index)
> {
> - CPUState *cs = CPU(ppc_env_get_cpu(env));
> + CPUPPCState *env = &cpu->env;
> uint64_t addr;
>
> addr = token + (index * HASH_PTE_SIZE_64) + HASH_PTE_SIZE_64/2;
> if (env->external_htab) {
> return ldq_p((const void *)(uintptr_t)addr);
> } else {
> - return ldq_phys(cs->as, addr);
> + return ldq_phys(CPU(cpu)->as, addr);
> }
> }
>
> diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
> index 5217691..0ab73bc 100644
> --- a/target-ppc/mmu_helper.c
> +++ b/target-ppc/mmu_helper.c
> @@ -1297,7 +1297,7 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf,
> CPUPPCState *env)
> case POWERPC_MMU_2_06a:
> case POWERPC_MMU_2_07:
> case POWERPC_MMU_2_07a:
> - dump_slb(f, cpu_fprintf, env);
> + dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env));
> break;
> #endif
> default:
> @@ -1439,12 +1439,12 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs,
> vaddr addr)
> case POWERPC_MMU_2_06a:
> case POWERPC_MMU_2_07:
> case POWERPC_MMU_2_07a:
> - return ppc_hash64_get_phys_page_debug(env, addr);
> + return ppc_hash64_get_phys_page_debug(cpu, addr);
> #endif
>
> case POWERPC_MMU_32B:
> case POWERPC_MMU_601:
> - return ppc_hash32_get_phys_page_debug(env, addr);
> + return ppc_hash32_get_phys_page_debug(cpu, addr);
>
> default:
> ;
> @@ -1510,6 +1510,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env,
> target_ulong address,
> int rw, int mmu_idx)
> {
> CPUState *cs = CPU(ppc_env_get_cpu(env));
> + PowerPCCPU *cpu = POWERPC_CPU(cs);
> mmu_ctx_t ctx;
> int access_type;
> int ret = 0;
> @@ -1611,9 +1612,9 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env,
> target_ulong address,
> tlb_miss:
> env->error_code |= ctx.key << 19;
> env->spr[SPR_HASH1] = env->htab_base +
> - get_pteg_offset32(env, ctx.hash[0]);
> + get_pteg_offset32(cpu, ctx.hash[0]);
> env->spr[SPR_HASH2] = env->htab_base +
> - get_pteg_offset32(env, ctx.hash[1]);
> + get_pteg_offset32(cpu, ctx.hash[1]);
> break;
> case POWERPC_MMU_SOFT_74xx:
> if (rw == 1) {
> @@ -2101,7 +2102,7 @@ void helper_store_sr(CPUPPCState *env, target_ulong
> srnum, target_ulong value)
> /* flags = flags */
> rs |= ((value >> 27) & 0xf) << 8;
>
> - ppc_store_slb(env, rb, rs);
> + ppc_store_slb(cpu, rb, rs);
> } else
> #endif
> if (env->sr[srnum] != value) {
>
- [Qemu-ppc] [PATCHv2 04/10] target-ppc: Rework SLB page size lookup, (continued)
- [Qemu-ppc] [PATCHv2 04/10] target-ppc: Rework SLB page size lookup, David Gibson, 2016/01/27
- [Qemu-ppc] [PATCHv2 09/10] target-ppc: Helper to determine page size information from hpte alone, David Gibson, 2016/01/27
- [Qemu-ppc] [PATCHv2 05/10] target-ppc: Use actual page size encodings from HPTE, David Gibson, 2016/01/27
- [Qemu-ppc] [PATCHv2 03/10] target-ppc: Rework ppc_store_slb, David Gibson, 2016/01/27
- [Qemu-ppc] [PATCHv2 02/10] target-ppc: Convert mmu-hash{32, 64}.[ch] from CPUPPCState to PowerPCCPU, David Gibson, 2016/01/27
- Re: [Qemu-ppc] [PATCHv2 02/10] target-ppc: Convert mmu-hash{32, 64}.[ch] from CPUPPCState to PowerPCCPU,
Laurent Vivier <=
- [Qemu-ppc] [PATCHv2 01/10] target-ppc: Remove unused kvmppc_read_segment_page_sizes() stub, David Gibson, 2016/01/27
- [Qemu-ppc] [PATCHv2 10/10] target-ppc: Allow more page sizes for POWER7 & POWER8 in TCG, David Gibson, 2016/01/27
- Re: [Qemu-ppc] [PATCHv2 00/10] Clean up page size handling for ppc 64-bit hash MMUs with TCG, Alexander Graf, 2016/01/28