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Re: [Qemu-ppc] [PATCH 03/10] target-ppc: Rework ppc_store_slb
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [PATCH 03/10] target-ppc: Rework ppc_store_slb |
Date: |
Wed, 27 Jan 2016 21:07:38 +1100 |
User-agent: |
Mutt/1.5.24 (2015-08-30) |
On Wed, Jan 27, 2016 at 08:32:25AM +0100, Thomas Huth wrote:
> On 27.01.2016 01:04, David Gibson wrote:
> > On Mon, Jan 25, 2016 at 08:22:51PM +0100, Alexander Graf wrote:
> >>
> >>
> >> On 01/25/2016 06:15 AM, David Gibson wrote:
> >>> ppc_store_slb updates the SLB for PPC cpus with 64-bit hash MMUs.
> >>> Currently it takes two parameters, which contain values encoded as the
> >>> register arguments to the slbmte instruction, one register contains the
> >>> ESID portion of the SLBE and also the slot number, the other contains the
> >>> VSID portion of the SLBE.
> >>>
> >>> We're shortly going to want to do some SLB updates from other code where
> >>> it is more convenient to supply the slot number and ESID separately, so
> >>> rework this function and its callers to work this way.
> >>>
> >>> As a bonus, this slightly simplifies the emulation of segment registers
> >>> for
> >>> when running a 32-bit OS on a 64-bit CPU.
> >>>
> >>> Signed-off-by: David Gibson <address@hidden>
> >>> ---
> >>> target-ppc/kvm.c | 2 +-
> >>> target-ppc/mmu-hash64.c | 24 +++++++++++++-----------
> >>> target-ppc/mmu-hash64.h | 3 ++-
> >>> target-ppc/mmu_helper.c | 14 +++++---------
> >>> 4 files changed, 21 insertions(+), 22 deletions(-)
> ...
> >>> @@ -196,7 +198,7 @@ void helper_store_slb(CPUPPCState *env, target_ulong
> >>> rb, target_ulong rs)
> >>> {
> >>> PowerPCCPU *cpu = ppc_env_get_cpu(env);
> >>> - if (ppc_store_slb(cpu, rb, rs) < 0) {
> >>> + if (ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfff, rs) < 0) {
> >>
> >> This might truncate the esid to 32bits on 32bits hosts, no? Should be
> >> 0xfffULL instead.
> >
> > Good point, nice catch.
>
> Are you sure that it is really needed? If I run the following test
> program on my 64-bit system:
>
> int main()
> {
> unsigned long long ll = -1ULL;
> printf("%llx %llx\n", ll, ll & ~0xfff);
> return 0;
> }
>
> Then I get this output:
>
> ffffffffffffffff fffffffffffff000
>
> So it sounds like the value is sign-extended when it is cast to
> 64-bit.
Ah, yes. It would be promoted to s64 and sign extended before being
promoted to u64. Still that's a pretty subtle detail to be relying on.
> However, if you respin this patch series anyway, then maybe better add
> the ULL for clarity.
Already done.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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[Qemu-ppc] [PATCH 07/10] target-ppc: Split 44x tlbiva from ppc_tlb_invalidate_one(), David Gibson, 2016/01/25
[Qemu-ppc] [PATCH 10/10] target-ppc: Allow more page sizes for POWER7 & POWER8 in TCG, David Gibson, 2016/01/25
[Qemu-ppc] [PATCH 09/10] target-ppc: Helper to determine page size information from hpte alone, David Gibson, 2016/01/25
[Qemu-ppc] [PATCH 05/10] target-ppc: Use actual page size encodings from HPTE, David Gibson, 2016/01/25
[Qemu-ppc] [PATCH 01/10] target-ppc: Remove unused kvmppc_read_segment_page_sizes() stub, David Gibson, 2016/01/25
[Qemu-ppc] [PATCH 08/10] target-ppc: Add new TLB invalidate by HPTE call for hash64 MMUs, David Gibson, 2016/01/25
[Qemu-ppc] [PATCH 04/10] target-ppc: Rework SLB page size lookup, David Gibson, 2016/01/25