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Re: [Qemu-ppc] [PATCH 5/9] target-ppc: Introduce TEXASRU Bit Fields
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From: |
Tom Musta |
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Subject: |
Re: [Qemu-ppc] [PATCH 5/9] target-ppc: Introduce TEXASRU Bit Fields |
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Date: |
Thu, 18 Dec 2014 12:41:13 -0600 |
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User-agent: |
Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 |
On 12/18/2014 12:29 PM, Alexander Graf wrote:
>
>
> On 18.12.14 19:10, Tom Musta wrote:
>> On 12/18/2014 11:02 AM, Alexander Graf wrote:
>>>
>>>
>>> On 18.12.14 17:34, Tom Musta wrote:
>>>> Define mnemonics for the various bit fields in the Transaction
>>>> EXception And Summary Register (TEXASR).
>>>
>>> This is missing an SoB line.
>>>
>>>
>>> Alex
>>>
>>
>> Sorry about that. I will publish a V2 but may wait a day or so for any
>> other other comments.
>
> The patches look good IMHO, just reply with your SoB line and I'll apply
> the rest too :)
>
>
> Alex
>
Signed-off-by: Tom Musta <address@hidden>
- [Qemu-ppc] [PATCH 0/9] target-ppc: Rudimentary Support for Transactional Memory, Tom Musta, 2014/12/18
- [Qemu-ppc] [PATCH 1/9] target-ppc: Introduce Instruction Type for Transactional Memory, Tom Musta, 2014/12/18
- [Qemu-ppc] [PATCH 3/9] target-ppc: Introduce tm_enabled Bit to CPU State, Tom Musta, 2014/12/18
- [Qemu-ppc] [PATCH 4/9] target-ppc: Power8 Supports Transactional Memory, Tom Musta, 2014/12/18
- [Qemu-ppc] [PATCH 2/9] target-ppc: Introduce Feature Flag for Transactional Memory, Tom Musta, 2014/12/18
- [Qemu-ppc] [PATCH 5/9] target-ppc: Introduce TEXASRU Bit Fields, Tom Musta, 2014/12/18
[Qemu-ppc] [PATCH 6/9] target-ppc: Introduce tbegin, Tom Musta, 2014/12/18
[Qemu-ppc] [PATCH 7/9] target-ppc: Introduce TM Noops, Tom Musta, 2014/12/18
[Qemu-ppc] [PATCH 8/9] target-ppc: Introduce tcheck, Tom Musta, 2014/12/18
[Qemu-ppc] [PATCH 9/9] target-ppc: Introduce Privileged TM Noops, Tom Musta, 2014/12/18
Re: [Qemu-ppc] [PATCH 0/9] target-ppc: Rudimentary Support for Transactional Memory, Alexander Graf, 2014/12/18