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Re: [Qemu-ppc] [PATCH 2/3] target-ppc : Add PPC_FLOAT_64 flag to instruc
From: |
Tom Musta |
Subject: |
Re: [Qemu-ppc] [PATCH 2/3] target-ppc : Add PPC_FLOAT_64 flag to instructions type |
Date: |
Wed, 10 Sep 2014 11:23:59 -0500 |
User-agent: |
Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 |
On 9/10/2014 4:18 AM, Alexander Graf wrote:
>
>
> On 10.09.14 07:03, Pierre Mallard wrote:
>> This patch declare a new floating point instruction flag PPC_FLOAT_64 to be
>> used
>> by fcfid, fctid[z] operations. Note that due to limited number of bit,
>> FSEL and FRES points now to same value, and PPC_FLOAT_64 to former FSEL
>> value.
>> (There seems to be no case where FSEL and FRES are not used together at the
>> moment)
>>
>> Signed-off-by: Pierre Mallard <address@hidden>
>> ---
>> target-ppc/cpu.h | 7 +++++--
>> target-ppc/translate_init.c | 2 +-
>> 2 files changed, 6 insertions(+), 3 deletions(-)
>>
>> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
>> index b64c652..b5b3912 100644
>> --- a/target-ppc/cpu.h
>> +++ b/target-ppc/cpu.h
>> @@ -1868,9 +1868,12 @@ enum {
>> PPC_FLOAT_FRES = 0x0000000000080000ULL,
>> PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
>> PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
>> - PPC_FLOAT_FSEL = 0x0000000000400000ULL,
>> + PPC_FLOAT_FSEL = 0x0000000000080000ULL,
>> PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
>>
>> + /* Use for PPC with double precision fpu */
>> + PPC_FLOAT_64 = 0x0000000000400000ULL,
>
> Please keep the list sorted by the bit number. Also I think we're better
> off not having the same bit used for 2 enums. Just keep PPC_FLOAT_FRES
> and make FSEL depend on the FRES bit in translate.c
>
Alternatively, you could add the new flag to PPC2_xxx .
>> +
>> /* Vector/SIMD extensions
>> */
>> /* Altivec support
>> */
>> PPC_ALTIVEC = 0x0000000001000000ULL,
>> @@ -1957,7 +1960,7 @@ enum {
>> | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
>> | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
>> | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
>> - | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
>> + | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | PPC_FLOAT_64 \
>> | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
>> | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
>> | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>> index b4dedce..073bef1 100644
>> --- a/target-ppc/translate_init.c
>> +++ b/target-ppc/translate_init.c
>> @@ -3899,7 +3899,7 @@ POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
>> pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
>> #ifdef PPC440x5_HAVE_FPU
>> PPC_FLOAT | PPC_FLOAT_FSQRT |
>> - PPC_FLOAT_STFIWX |
>> + PPC_FLOAT_STFIWX | PPC_FLOAT_64 |
>> #endif
>> PPC_DCR | PPC_WRTEE | PPC_RFMCI |
>> PPC_CACHE | PPC_CACHE_ICBI |
>>