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Re: [Qemu-ppc] [PATCH 11/17] ppc: rename gen_set_cr6_from_fpscr
From: |
Tom Musta |
Subject: |
Re: [Qemu-ppc] [PATCH 11/17] ppc: rename gen_set_cr6_from_fpscr |
Date: |
Wed, 03 Sep 2014 14:41:18 -0500 |
User-agent: |
Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 |
On 8/28/2014 12:15 PM, Paolo Bonzini wrote:
> It sets CR1, not CR6 (and the spec agrees).
>
> Signed-off-by: Paolo Bonzini <address@hidden>
> ---
> target-ppc/translate.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 8def0ae..67f13f7 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -8179,7 +8179,7 @@ static inline TCGv_ptr gen_fprp_ptr(int reg)
> }
>
> #if defined(TARGET_PPC64)
> -static void gen_set_cr6_from_fpscr(DisasContext *ctx)
> +static void gen_set_cr1_from_fpscr(DisasContext *ctx)
> {
> TCGv_i32 tmp = tcg_temp_new_i32();
> tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
> @@ -8187,7 +8187,7 @@ static void gen_set_cr6_from_fpscr(DisasContext *ctx)
> tcg_temp_free_i32(tmp);
> }
> #else
> -static void gen_set_cr6_from_fpscr(DisasContext *ctx)
> +static void gen_set_cr1_from_fpscr(DisasContext *ctx)
> {
> gen_op_mtcr(4, cpu_fpscr, 28);
> }
> @@ -8207,7 +8207,7 @@ static void gen_##name(DisasContext *ctx) \
> rb = gen_fprp_ptr(rB(ctx->opcode)); \
> gen_helper_##name(cpu_env, rd, ra, rb); \
> if (unlikely(Rc(ctx->opcode) != 0)) { \
> - gen_set_cr6_from_fpscr(ctx); \
> + gen_set_cr1_from_fpscr(ctx); \
> } \
> tcg_temp_free_ptr(rd); \
> tcg_temp_free_ptr(ra); \
> @@ -8265,7 +8265,7 @@ static void gen_##name(DisasContext *ctx) \
> u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
> gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
> if (unlikely(Rc(ctx->opcode) != 0)) { \
> - gen_set_cr6_from_fpscr(ctx); \
> + gen_set_cr1_from_fpscr(ctx); \
> } \
> tcg_temp_free_ptr(rt); \
> tcg_temp_free_ptr(rb); \
> @@ -8289,7 +8289,7 @@ static void gen_##name(DisasContext *ctx) \
> i32 = tcg_const_i32(i32fld(ctx->opcode)); \
> gen_helper_##name(cpu_env, rt, ra, rb, i32); \
> if (unlikely(Rc(ctx->opcode) != 0)) { \
> - gen_set_cr6_from_fpscr(ctx); \
> + gen_set_cr1_from_fpscr(ctx); \
> } \
> tcg_temp_free_ptr(rt); \
> tcg_temp_free_ptr(rb); \
> @@ -8310,7 +8310,7 @@ static void gen_##name(DisasContext *ctx) \
> rb = gen_fprp_ptr(rB(ctx->opcode)); \
> gen_helper_##name(cpu_env, rt, rb); \
> if (unlikely(Rc(ctx->opcode) != 0)) { \
> - gen_set_cr6_from_fpscr(ctx); \
> + gen_set_cr1_from_fpscr(ctx); \
> } \
> tcg_temp_free_ptr(rt); \
> tcg_temp_free_ptr(rb); \
> @@ -8331,7 +8331,7 @@ static void gen_##name(DisasContext *ctx) \
> i32 = tcg_const_i32(i32fld(ctx->opcode)); \
> gen_helper_##name(cpu_env, rt, rs, i32); \
> if (unlikely(Rc(ctx->opcode) != 0)) { \
> - gen_set_cr6_from_fpscr(ctx); \
> + gen_set_cr1_from_fpscr(ctx); \
> } \
> tcg_temp_free_ptr(rt); \
> tcg_temp_free_ptr(rs); \
>
Reviewed-by: Tom Musta <address@hidden>
Tested-by: Tom Musta <address@hidden>
- Re: [Qemu-ppc] [PATCH 11/17] ppc: rename gen_set_cr6_from_fpscr,
Tom Musta <=