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[Qemu-ppc] [PATCH v5 23/30] target-ppc: Add POWER8's MMCR2/MMCRS SPRs
From: |
Alexey Kardashevskiy |
Subject: |
[Qemu-ppc] [PATCH v5 23/30] target-ppc: Add POWER8's MMCR2/MMCRS SPRs |
Date: |
Wed, 4 Jun 2014 22:50:58 +1000 |
This adds POWER8 specific PMU MMCR2/MMCRS SPRs.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
---
Changes:
v5:
* s/gen_spr_power8_pmu_hypv/gen_spr_power8_pmu_sup/
* moved write_ureg in earlier patch
v4:
* disabled write_ureg for user mode, privileged mode is still needed for
recent guest kernels to boot on POWER8
---
target-ppc/cpu.h | 3 +++
target-ppc/translate_init.c | 22 ++++++++++++++++++++++
2 files changed, 25 insertions(+)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 7d566f3..8a27331 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1480,6 +1480,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_MPC_MI_CTR (0x300)
#define SPR_PERF1 (0x301)
#define SPR_RCPU_MI_RBA1 (0x301)
+#define SPR_POWER_UMMCR2 (0x301)
#define SPR_PERF2 (0x302)
#define SPR_RCPU_MI_RBA2 (0x302)
#define SPR_MPC_MI_AP (0x302)
@@ -1527,6 +1528,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_MPC_MD_TW (0x30F)
#define SPR_UPERF0 (0x310)
#define SPR_UPERF1 (0x311)
+#define SPR_POWER_MMCR2 (0x311)
#define SPR_UPERF2 (0x312)
#define SPR_POWER_MMCRA (0X312)
#define SPR_UPERF3 (0x313)
@@ -1579,6 +1581,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_440_ITV3 (0x377)
#define SPR_440_CCR1 (0x378)
#define SPR_DCRIPR (0x37B)
+#define SPR_POWER_MMCRS (0x37E)
#define SPR_PPR (0x380)
#define SPR_750_GQR0 (0x390)
#define SPR_440_DNV0 (0x390)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 30ae66a..548b582 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7507,6 +7507,26 @@ static void gen_spr_970_pmu_user(CPUPPCState *env)
0x00000000);
}
+static void gen_spr_power8_pmu_sup(CPUPPCState *env)
+{
+ spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_MMCR2, 0x00000000);
+ spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_MMCRS, 0x00000000);
+}
+
+static void gen_spr_power8_pmu_user(CPUPPCState *env)
+{
+ spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, &spr_write_ureg,
+ 0x00000000);
+}
+
static void gen_spr_power5p_ear(CPUPPCState *env)
{
/* External access control */
@@ -7673,6 +7693,8 @@ static void init_proc_book3s_64(CPUPPCState *env, int
version)
gen_spr_power8_tce_address_control(env);
gen_spr_power8_ids(env);
gen_spr_power8_fscr(env);
+ gen_spr_power8_pmu_sup(env);
+ gen_spr_power8_pmu_user(env);
}
#if !defined(CONFIG_USER_ONLY)
switch (version) {
--
2.0.0
- [Qemu-ppc] [PATCH v5 08/30] target-ppc: Add PMC7/8 to 970 class, (continued)
- [Qemu-ppc] [PATCH v5 08/30] target-ppc: Add PMC7/8 to 970 class, Alexey Kardashevskiy, 2014/06/04
- [Qemu-ppc] [PATCH v5 07/30] target-ppc: Add PMC5/6, SDAR and MMCRA to 970 family, Alexey Kardashevskiy, 2014/06/04
- [Qemu-ppc] [PATCH v5 12/30] target-ppc: Enable PMU SPRs migration, Alexey Kardashevskiy, 2014/06/04
- [Qemu-ppc] [PATCH v5 10/30] target-ppc: Introduce and reuse generalized init_proc_book3s_64(), Alexey Kardashevskiy, 2014/06/04
- [Qemu-ppc] [PATCH v5 13/30] target-ppc: Move POWER7/8 PIR/PURR/SPURR SPR registration to helpers, Alexey Kardashevskiy, 2014/06/04
- [Qemu-ppc] [PATCH v5 14/30] target-ppc: Move POWER8 TCE Address control (TAR) to a helper, Alexey Kardashevskiy, 2014/06/04
- [Qemu-ppc] [PATCH v5 25/30] KVM: target-ppc: Enable TM state migration, Alexey Kardashevskiy, 2014/06/04
- [Qemu-ppc] [PATCH v5 23/30] target-ppc: Add POWER8's MMCR2/MMCRS SPRs,
Alexey Kardashevskiy <=
- [Qemu-ppc] [PATCH v5 16/30] target-ppc: Make use of gen_spr_book3s_altivec() for POWER7/8, Alexey Kardashevskiy, 2014/06/04
- [Qemu-ppc] [PATCH v5 21/30] target-ppc: Add POWER8's FSCR SPR, Alexey Kardashevskiy, 2014/06/04
- [Qemu-ppc] [PATCH v5 15/30] target-ppc: Move POWER7/8 CFAR/DSCR/CTRL/PPR/PCR SPR registration to helpers, Alexey Kardashevskiy, 2014/06/04
- [Qemu-ppc] [PATCH v5 19/30] target-ppc: Refactor class init for POWER7/8, Alexey Kardashevskiy, 2014/06/04
- [Qemu-ppc] [PATCH v5 18/30] target-ppc: Switch POWER7/8 classes to use correct PMU SPRs, Alexey Kardashevskiy, 2014/06/04
- [Qemu-ppc] [PATCH v5 17/30] target-ppc: Make use of gen_spr_power5p_lpar() for POWER7/8, Alexey Kardashevskiy, 2014/06/04
- [Qemu-ppc] [PATCH v5 20/30] target-ppc: Add POWER8's TIR SPR, Alexey Kardashevskiy, 2014/06/04