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[Qemu-ppc] [PULL 059/118] KVM: PPC: Don't secretly add 1T segment featur
From: |
Alexander Graf |
Subject: |
[Qemu-ppc] [PULL 059/118] KVM: PPC: Don't secretly add 1T segment feature to CPU |
Date: |
Wed, 4 Jun 2014 14:44:00 +0200 |
When we select a CPU type that does not support 1TB segments, we should
not expose 1TB just because KVM supports 1TB segments. User configuration
always wins over feature availability.
Signed-off-by: Alexander Graf <address@hidden>
---
target-ppc/kvm.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index 3569367..0744f51 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -356,6 +356,10 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
/* Convert to QEMU form */
memset(&env->sps, 0, sizeof(env->sps));
+ /*
+ * XXX This loop should be an entry wide AND of the capabilities that
+ * the selected CPU has with the capabilities that KVM supports.
+ */
for (ik = iq = 0; ik < KVM_PPC_PAGE_SIZES_MAX_SZ; ik++) {
struct ppc_one_seg_page_size *qsps = &env->sps.sps[iq];
struct kvm_ppc_one_seg_page_size *ksps = &smmu_info.sps[ik];
@@ -382,9 +386,7 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
}
}
env->slb_nr = smmu_info.slb_size;
- if (smmu_info.flags & KVM_PPC_1T_SEGMENTS) {
- env->mmu_model |= POWERPC_MMU_1TSEG;
- } else {
+ if (!(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) {
env->mmu_model &= ~POWERPC_MMU_1TSEG;
}
}
--
1.8.1.4
- [Qemu-ppc] [PULL 034/118] target-ppc: Introduce DFP Divide, (continued)
- [Qemu-ppc] [PULL 034/118] target-ppc: Introduce DFP Divide, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 046/118] target-ppc: Introduce DFP Convert to Fixed, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 054/118] util: Add AES ShiftRows and InvShiftRows Tables, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 056/118] target-i386: Use Common ShiftRows and InvShiftRows Tables, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 052/118] spapr_pci: fix MSI limit, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 053/118] util: Add S-Box and InvS-Box Arrays to Common AES Utils, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 048/118] target-ppc: Introduce DFP Encode BCD to DPD, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 071/118] PPC: Add u-boot firmware for e500, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 015/118] libdecnumber: Introduce libdecnumber Code, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 057/118] target-arm: Use Common Tables in AES Instructions, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 059/118] KVM: PPC: Don't secretly add 1T segment feature to CPU,
Alexander Graf <=
- [Qemu-ppc] [PULL 066/118] PPC: Fix SPR access control of L1CFG0, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 074/118] spapr: Add ibm, chip-id property in device tree, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 073/118] spapr: Add support for time base offset migration, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 027/118] target-ppc: Introduce Generator Macros for DFP Arithmetic Forms, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 061/118] PPC: e500: implement PCI INTx routing, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 064/118] PPC: Make all e500 CPUs SVR aware, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 050/118] target-ppc: Introduce DFP Insert Biased Exponent, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 058/118] target-ppc: Refactor AES Instructions, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 075/118] macio: handle non-block ATAPI DMA transfers, Alexander Graf, 2014/06/04