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Re: [Qemu-ppc] [PATCH 5/9] target-ppc: Add POWER8 SPRs

From: Alexander Graf
Subject: Re: [Qemu-ppc] [PATCH 5/9] target-ppc: Add POWER8 SPRs
Date: Tue, 27 May 2014 02:26:51 +0200
User-agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.9; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 

On 27.05.14 02:23, Alexey Kardashevskiy wrote:

On 05/27/2014 06:09 AM, Alexander Graf wrote:

On 26.05.14 17:45, Alexey Kardashevskiy wrote:

On 05/22/2014 04:08 AM, Tom Musta wrote:

On 5/21/2014 1:20 AM, Alexey Kardashevskiy wrote:

This adds helper which adds TAR/BESCRS/BESCRSU/BESCRR/BESCRRU/
EBBHR/EBBRR/BESCR/TFHAR/TFIAR/TEXASR/TEXASRU SPRs.

This adds MMCR2/FSCR/MMCRS SPRs.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
---
   target-ppc/cpu.h            |  15 ++++++
   target-ppc/translate_init.c | 123
++++++++++++++++++++++++++++++++++----------
   2 files changed, 112 insertions(+), 26 deletions(-)

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 262cf0f..72ed763 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1258,6 +1258,10 @@ static inline int cpu_mmu_index (CPUPPCState *env)
   #define SPR_MPC_EIE           (0x050)
   #define SPR_MPC_EID           (0x051)
   #define SPR_MPC_NRI           (0x052)
+#define SPR_TFHAR             (0x080)
+#define SPR_TFIAR             (0x081)
+#define SPR_TEXASR            (0x082)
+#define SPR_TEXASRU           (0x083)
   #define SPR_UCTRL             (0x088)
   #define SPR_MPC_CMPA          (0x090)
   #define SPR_MPC_CMPB          (0x091)
@@ -1270,6 +1274,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
   #define SPR_CTRL              (0x098)
   #define SPR_MPC_CMPE          (0x098)
   #define SPR_MPC_CMPF          (0x099)
+#define SPR_FSCR              (0x099)
   #define SPR_MPC_CMPG          (0x09A)
   #define SPR_MPC_CMPH          (0x09B)
   #define SPR_MPC_LCTRL1        (0x09C)
@@ -1461,6 +1466,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
   #define SPR_MPC_MI_CTR        (0x300)
   #define SPR_PERF1             (0x301)
   #define SPR_RCPU_MI_RBA1      (0x301)
+#define SPR_POWER_UMMCR2      (0x301)
   #define SPR_PERF2             (0x302)
   #define SPR_RCPU_MI_RBA2      (0x302)
   #define SPR_MPC_MI_AP         (0x302)
@@ -1500,6 +1506,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
   #define SPR_MPC_MD_TW         (0x30F)
   #define SPR_UPERF0            (0x310)
   #define SPR_UPERF1            (0x311)
+#define SPR_POWER_MMCR2       (0x311)
   #define SPR_UPERF2            (0x312)
   #define SPR_MMCRA             (0x312)
   #define SPR_UPERF3            (0x313)
@@ -1519,11 +1526,18 @@ static inline int cpu_mmu_index (CPUPPCState *env)
   #define SPR_UPERFF            (0x31F)
   #define SPR_RCPU_MI_RA0       (0x320)
   #define SPR_MPC_MI_DBCAM      (0x320)
+#define SPR_BESCRS            (0x320)
   #define SPR_RCPU_MI_RA1       (0x321)
   #define SPR_MPC_MI_DBRAM0     (0x321)
+#define SPR_BESCRSU           (0x321)
   #define SPR_RCPU_MI_RA2       (0x322)
   #define SPR_MPC_MI_DBRAM1     (0x322)
+#define SPR_BESCRR            (0x322)
   #define SPR_RCPU_MI_RA3       (0x323)
+#define SPR_BESCRRU           (0x323)
+#define SPR_EBBHR             (0x324)
+#define SPR_EBBRR             (0x325)
+#define SPR_BESCR             (0x326)
   #define SPR_RCPU_L2U_RA0      (0x328)
   #define SPR_MPC_MD_DBCAM      (0x328)
   #define SPR_RCPU_L2U_RA1      (0x329)
@@ -1542,6 +1556,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
   #define SPR_440_ITV3          (0x377)
   #define SPR_440_CCR1          (0x378)
   #define SPR_DCRIPR            (0x37B)
+#define SPR_MMCRS             (0x37E)
   #define SPR_PPR               (0x380)
   #define SPR_750_GQR0          (0x390)
   #define SPR_440_DNV0          (0x390)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 3c37e93..d23fcc6 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7951,37 +7951,108 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void
*data)
       pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
   }
   -static void init_proc_POWER8(CPUPPCState *env)
+static void get_spr_power8_branch_control(CPUPPCState *env)
   {
-    gen_spr_ne_601(env);
-    gen_spr_7xx(env);
-    /* Time base */
-    gen_tbl(env);
-    gen_spr_book3s_ids(env);
-    gen_spr_book3s_common(env);
-    gen_spr_amr(env);
-    gen_spr_book3s_vr(env);
-    gen_spr_book3s_lpar(env);
-    gen_spr_book3s_purr(env);
-    gen_spr_book3s_debug(env);
-    gen_spr_book3s_pmu(env);
-#if !defined(CONFIG_USER_ONLY)
-    env->slb_nr = 32;
-#endif /* !CONFIG_USER_ONLY */
-    init_excp_POWER7(env);
-    env->dcache_line_size = 128;
-    env->icache_line_size = 128;
-
-    /* Allocate hardware IRQ controller */
-    ppcPOWER7_irq_init(env);
-    /* Can't find information on what this should be on reset.  This
-     * value is the one used by 74xx processors. */
-    vscr_init(env, 0x00010000);
-
       spr_register(env, SPR_TAR, "TAR",
                    &spr_read_generic, &spr_write_generic,
                    &spr_read_generic, &spr_write_generic,
                    0x00000000);
+
+    spr_register(env, SPR_BESCRS, "BESCRS",
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 &spr_read_generic, &spr_write_generic,
+                 0x00000000);
+    spr_register(env, SPR_BESCRSU, "BESCRSU",
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 &spr_read_generic, &spr_write_generic,
+                 0x00000000);
+    spr_register(env, SPR_BESCRR, "BESCRR",
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 &spr_read_generic, &spr_write_generic,
+                 0x00000000);
+    spr_register(env, SPR_BESCRRU, "BESCRRU",
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 &spr_read_generic, &spr_write_generic,
+                 0x00000000);
+    spr_register_kvm(env, SPR_EBBHR, "EBBHR",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_EBBHR, 0x00000000);
+    spr_register_kvm(env, SPR_EBBRR, "EBBRR",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_EBBRR, 0x00000000);
+    spr_register_kvm(env, SPR_BESCR, "BESCR",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_BESCR, 0x00000000);
+}

These are all user-mode accessible, no?


+
+static void get_spr_power8_tm(CPUPPCState *env)
+{
+    spr_register_kvm(env, SPR_TFHAR, "TFHAR",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_TFHAR, 0x00000000);
+    spr_register_kvm(env, SPR_TFIAR, "TFIAR",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_TFIAR, 0x00000000);
+    spr_register_kvm(env, SPR_TEXASR, "TEXASR",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_TEXASR, 0x00000000);
+    spr_register(env, SPR_TEXASRU, "TEXASRU",
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 &spr_read_generic, &spr_write_generic,
+                 0x00000000);
+}

Same comment.

Also, the xxxU SPRs numbers refer to the upper half of 64-bit SPRs.
These are necessary
to support access on 32-bit implementations.  It seems like some special
spr access routines
are required to support this.

I am not familiar with TCG (yet)... Something like below? This uses the
fact that SPRs go consequently.


static void spr_read_upper32(void *opaque, int gprn, int sprn)
{
      TCGv spr64 = tcg_temp_new();

      gen_load_spr(spr64, sprn - 1);

gen_load_spr() takes a GPR as argument, no?

No. Here it is:

static TCGv cpu_gpr[32];
...
static inline void gen_load_spr(TCGv t, int reg)
{
     tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
}
...
static void spr_read_generic (void *opaque, int gprn, int sprn)
{
     gen_load_spr(cpu_gpr[gprn], sprn);
     spr_load_dump_spr(sprn);
}


Ah, I must've looked at the wrong function then.



TCGv is a type of the first parameter of gen_load_spr(), why would it care
if it is GPR or not?

How does this all work? One global static array of GPRs? No SMP whatsoever?
Or there is some trick?
It's a global static array of TCG variables that reference env + static offset :). Env stays dynamic, the only thing that's global is the offset. 


What is opaque for here? This TCG business is behind my understanding yet :)


Apparently unused in this case :)


Alex
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