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[Qemu-ppc] [PATCH 1/9] target-ppc: Rename MMCR0/1 contants
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From: |
Alexey Kardashevskiy |
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Subject: |
[Qemu-ppc] [PATCH 1/9] target-ppc: Rename MMCR0/1 contants |
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Date: |
Wed, 21 May 2014 16:20:20 +1000 |
MMCR0 and MMCR1 have different numbers for 32 and 64 bit POWERPC.
We are going to support 64bit versions too so let's rename 32bit ones
to avoid confusion.
604 uses same SPR number for MMCR0 so it is included in this patch too.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
---
target-ppc/cpu.h | 8 ++++----
target-ppc/translate_init.c | 12 ++++++------
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index b035e91..13eea19 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1567,11 +1567,11 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_UPMC5 (0x3A1)
#define SPR_UPMC6 (0x3A2)
#define SPR_UBAMR (0x3A7)
-#define SPR_UMMCR0 (0x3A8)
+#define SPR_7XX_UMMCR0 (0x3A8)
#define SPR_UPMC1 (0x3A9)
#define SPR_UPMC2 (0x3AA)
#define SPR_USIAR (0x3AB)
-#define SPR_UMMCR1 (0x3AC)
+#define SPR_7XX_UMMCR1 (0x3AC)
#define SPR_UPMC3 (0x3AD)
#define SPR_UPMC4 (0x3AE)
#define SPR_USDA (0x3AF)
@@ -1590,14 +1590,14 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_405_DVC1 (0x3B6)
#define SPR_405_DVC2 (0x3B7)
#define SPR_BAMR (0x3B7)
-#define SPR_MMCR0 (0x3B8)
+#define SPR_7XX_MMCR0 (0x3B8)
#define SPR_PMC1 (0x3B9)
#define SPR_40x_SGR (0x3B9)
#define SPR_PMC2 (0x3BA)
#define SPR_40x_DCWR (0x3BA)
#define SPR_SIAR (0x3BB)
#define SPR_405_SLER (0x3BB)
-#define SPR_MMCR1 (0x3BC)
+#define SPR_7XX_MMCR1 (0x3BC)
#define SPR_405_SU0R (0x3BC)
#define SPR_401_SKR (0x3BC)
#define SPR_PMC3 (0x3BD)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 16ecada..bf5ea09 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -951,12 +951,12 @@ static void gen_spr_7xx (CPUPPCState *env)
0x00000000);
/* Performance monitors */
/* XXX : not implemented */
- spr_register(env, SPR_MMCR0, "MMCR0",
+ spr_register(env, SPR_7XX_MMCR0, "MMCR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_MMCR1, "MMCR1",
+ spr_register(env, SPR_7XX_MMCR1, "MMCR1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
@@ -986,12 +986,12 @@ static void gen_spr_7xx (CPUPPCState *env)
&spr_read_generic, SPR_NOACCESS,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_UMMCR0, "UMMCR0",
+ spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_UMMCR1, "UMMCR1",
+ spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
@@ -1117,7 +1117,7 @@ static void gen_spr_604 (CPUPPCState *env)
KVM_REG_PPC_DABR, 0x00000000);
/* Performance counters */
/* XXX : not implemented */
- spr_register(env, SPR_MMCR0, "MMCR0",
+ spr_register(env, SPR_7XX_MMCR0, "MMCR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
@@ -5436,7 +5436,7 @@ static void init_proc_604E (CPUPPCState *env)
gen_spr_ne_601(env);
gen_spr_604(env);
/* XXX : not implemented */
- spr_register(env, SPR_MMCR1, "MMCR1",
+ spr_register(env, SPR_7XX_MMCR1, "MMCR1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
--
1.9.rc0