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[Qemu-ppc] [PULL 049/130] target-ppc: Floating Merge Word Instructions
From: |
Alexander Graf |
Subject: |
[Qemu-ppc] [PULL 049/130] target-ppc: Floating Merge Word Instructions |
Date: |
Fri, 7 Mar 2014 00:32:56 +0100 |
From: Tom Musta <address@hidden>
This patch adds the Floating Merge Even Word (fmrgew) and Floating
Merge Odd Word (fmrgow) instructions.
Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
target-ppc/translate.c | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index bc608ee..c6a357a 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2294,6 +2294,32 @@ static void gen_fcpsgn(DisasContext *ctx)
gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
}
+static void gen_fmrgew(DisasContext *ctx)
+{
+ TCGv_i64 b0;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ b0 = tcg_temp_new_i64();
+ tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
+ tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
+ b0, 0, 32);
+ tcg_temp_free_i64(b0);
+}
+
+static void gen_fmrgow(DisasContext *ctx)
+{
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
+ cpu_fpr[rB(ctx->opcode)],
+ cpu_fpr[rA(ctx->opcode)],
+ 32, 32);
+}
+
/*** Floating-Point status & ctrl register ***/
/* mcrfs */
@@ -9414,6 +9440,8 @@ GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
+GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
+GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
--
1.8.1.4
- [Qemu-ppc] [PULL 039/130] target-ppc: VSX Stage 4: Add xsaddsp and xssubsp, (continued)
- [Qemu-ppc] [PULL 039/130] target-ppc: VSX Stage 4: Add xsaddsp and xssubsp, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 057/130] target-ppc: Add ISA 2.06 divwe[o] Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 033/130] target-ppc: Add VSX Rounding Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 043/130] target-ppc: VSX Stage 4: Add xssqrtsp, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 056/130] target-ppc: Add ISA 2.06 divweu[o] Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 047/130] target-ppc: VSX Stage 4: Add xxleqv, xxlnand and xxlorc, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 041/130] target-ppc: VSX Stage 4: Add xsdivsp, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 023/130] target-ppc: Add VSX ISA2.06 xsqrt Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 022/130] target-ppc: Add VSX ISA2.06 xre Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 038/130] target-ppc: VSX Stage 4: Add stxsiwx and stxsspx, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 049/130] target-ppc: Floating Merge Word Instructions,
Alexander Graf <=
- [Qemu-ppc] [PULL 119/130] spapr-vlan: flush queue whenever can_receive can go from false to true, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 037/130] target-ppc: VSX Stage 4: Refactor stxsdx, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 034/130] target-ppc: VSX Stage 4: Add VSX 2.07 Flag, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 036/130] target-ppc: VSX Stage 4: Add lxsiwax, lxsiwzx and lxsspx, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 024/130] target-ppc: Add VSX ISA2.06 xrsqrte Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 008/130] kvm: Add a new machine option kvm-type, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 013/130] PPC: KVM: add support for LPCR, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 130/130] target-ppc: spapr: e500: fix to use cpu_dt_id, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 113/130] target-ppc: Altivec 2.07: Vector Gather Bits by Bytes, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 115/130] target-ppc: Altivec 2.07: Binary Coded Decimal Instructions, Alexander Graf, 2014/03/06