Re: [Qemu-ppc] [Qemu-devel] [V3 PATCH 02/14] target-ppc: Add ISA2.06 bpermd Instruction

[Scott Wood]

On Wed, 2013-12-18 at 14:48 -0600, Tom Musta wrote:
> This patch adds the Bit Permute Doubleword (bpermd) instruction,
> which was introduced in Power ISA 2.06 as part of the base 64-bit
> architecture.

Technically it's "Category: Embedded.Phased-in, Server" rather than
"Category: Base".  e5500 does have it, though, so if IBM's 64-bit booke
chips also have it, it might as well be Base.

> V2: Addressing stylistic comments from Richard Henderson.
> 
> Signed-off-by: Tom Musta <address@hidden>
> Reviewed-by: Richard Henderson <address@hidden>
> ---
>  target-ppc/helper.h     |    1 +
>  target-ppc/int_helper.c |   20 ++++++++++++++++++++
>  target-ppc/translate.c  |   10 ++++++++++
>  3 files changed, 31 insertions(+), 0 deletions(-)
> 
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 6250eba..1ec9c65 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -41,6 +41,7 @@ DEF_HELPER_3(sraw, tl, env, tl, tl)
>  #if defined(TARGET_PPC64)
>  DEF_HELPER_FLAGS_1(cntlzd, TCG_CALL_NO_RWG_SE, tl, tl)
>  DEF_HELPER_FLAGS_1(popcntd, TCG_CALL_NO_RWG_SE, tl, tl)
> +DEF_HELPER_3(bpermd, i64, env, i64, i64)
>  DEF_HELPER_3(srad, tl, env, tl, tl)
>  #endif
>  
> diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
> index e50bdd2..abc69a7 100644
> --- a/target-ppc/int_helper.c
> +++ b/target-ppc/int_helper.c
> @@ -53,6 +53,26 @@ target_ulong helper_cntlzd(target_ulong t)
>  }
>  #endif
>  
> +#if defined(TARGET_PPC64)
> +
> +uint64_t helper_bpermd(CPUPPCState *env, uint64_t rs, uint64_t rb)
> +{
> +    int i;
> +    uint64_t ra = 0;
> +
> +    for (i = 0; i < 8; i++) {
> +        int index = (rs >> (i*8)) & 0xFF;
> +        if (index < 64) {
> +            if (rb & (1ul << (63-index))) {

1ull

Don't assume that the host is 64-bit

-Scott