Re: [Qemu-ppc] [Qemu-devel] [PATCH 12/14] VSX Stage 4: Add Scalar SP Fused Multiply-Adds

[Richard Henderson]

On 11/08/2013 09:28 AM, Richard Henderson wrote:
> On 11/07/2013 06:31 AM, Tom Musta wrote:
>>          }                                                                   
>>   \
>> +                                                                            
>>   \
>> +        if (r2sp) {                                                         
>>   \
>> +            float32 tmp32 = float64_to_float32(xt_out.fld[i],               
>>   \
>> +                                               &env->fp_status);            
>>   \
>> +            xt_out.fld[i] = float32_to_float64(tmp32, &env->fp_status);     
>>   \
>> +        }                                                                   
>>   \
>> +                                                                            
>>   \
> 
> You can't get correct results for a single-precision fma from a
> double-precision fma and merely rounding the results.
> 
> See e.g. glibc's sysdeps/ieee754/dbl-64/s_fmaf.c.

Blah, nevermind.  That would be using separate add+mul in double-precision, not
using a double-precision fma primitive.


r~