Re: [Qemu-ppc] [PATCH 7/7] Add xxpermdi

[Alexander Graf]

On 25.09.2013, at 15:35, Tom Musta wrote:

> This patch adds the xxpermdi instruction.  The instruction
> uses bits 22, 23, 29 and 30 for non-opcode fields (DM, AX
> and BX).  This results in overloading of the opcode table
> with aliases, which can be seen in the GEN_XX3FORM_DM
> macro.
> 
> Amended: fixed bug in second "if-else" sequence so that it
> correctly writes to the lower half of the target VSR.
> 
> Signed-off-by: Tom Musta <address@hidden>

Anton, could you please review and ack? :)


Alex

> 
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index a46958b..725f74a 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -7039,6 +7039,25 @@ static void gen_stxvd2x(DisasContext *ctx)
>     tcg_temp_free(EA);
> }
> 
> +static void gen_xxpermdi(DisasContext *ctx)
> +{
> +    if (unlikely(!ctx->vsx_enabled)) {
> +        gen_exception(ctx, POWERPC_EXCP_VSXU);
> +        return;
> +    }
> +
> +    if ((DM(ctx->opcode) & 2) == 0) {
> +        tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), 
> cpu_vsrh(xA(ctx->opcode)));
> +    } else {
> +        tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), 
> cpu_vsrl(xA(ctx->opcode)));
> +    }
> +    if ((DM(ctx->opcode) & 1) == 0) {
> +        tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), 
> cpu_vsrh(xB(ctx->opcode)));
> +    } else {
> +        tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), 
> cpu_vsrl(xB(ctx->opcode)));
> +    }
> +}
> +
> /***                           SPE extension                               
> ***/
> /* Register moves */
> 
> @@ -9500,6 +9519,26 @@ GEN_VSX_LXVNX(d2x, 0x0C, 0x1A),
> 
> GEN_VSX_STXVNX(d2x, 0x0C, 0x1E),
> 
> +#undef GEN_XX3FORM_DM
> +#define GEN_XX3FORM_DM(name, opc2, opc3) \
> +GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, 
> PPC2_VSX),\
> +GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, 
> PPC2_VSX),\
> +GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, 
> PPC2_VSX),\
> +GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, 
> PPC2_VSX),\
> +GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, 
> PPC2_VSX),\
> +GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, 
> PPC2_VSX),\
> +GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, 
> PPC2_VSX),\
> +GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, 
> PPC2_VSX),\
> +GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, 
> PPC2_VSX),\
> +GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, 
> PPC2_VSX),\
> +GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, 
> PPC2_VSX),\
> +GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, 
> PPC2_VSX),\
> +GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, 
> PPC2_VSX),\
> +GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, 
> PPC2_VSX),\
> +GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, 
> PPC2_VSX),\
> +GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, 
> PPC2_VSX)
> +
> +GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
> 
> #undef GEN_SPE
> #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
> -- 
> 1.7.1
> 
> 
>