Re: [Qemu-ppc] VSX Instruction Set Implementation

[Alexander Graf]

On 15.08.2013, at 21:23, Jacques Mony wrote:

> Hi,
> 
> Going through the code, I believe I started gathering the logic. However, 
> there is one piece that I just can't quite understand (and it's probably so 
> obvious):
> 
> In translate.c, GEN_HANDLER (which is actually GEN_OPCODE)... is used in the 
> following manner:
> 
> GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
> 
> I believe I get the meaning of first parameter (the instruction name), the 
> second one (0x1F -> primary opcode 31 - right ?), then I assume the last one 
> to be categories). However, the 3 numeric parameters just make no sense to 
> me. I tried mapping them as secondary opcode values, masks for opc2 and opc3 
> in the instruction, I just can't find where this comes from...
> 
> Can someone point me in the right direction, please?

Sure. Check out this code:

/*****************************************************************************/
/***                           Instruction decoding                        ***/
#define EXTRACT_HELPER(name, shift, nb)                                       \
static inline uint32_t name(uint32_t opcode)                                  \
{                                                                             \
    return (opcode >> (shift)) & ((1 << (nb)) - 1);                           \
}

#define EXTRACT_SHELPER(name, shift, nb)                                      \
static inline int32_t name(uint32_t opcode)                                   \
{                                                                             \
    return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1));                \
}

/* Opcode part 1 */
EXTRACT_HELPER(opc1, 26, 6);
/* Opcode part 2 */
EXTRACT_HELPER(opc2, 1, 5);
/* Opcode part 3 */
EXTRACT_HELPER(opc3, 6, 5);


The first 3 numbers are opc1, opc2 and opc3, followed by a reserved bit mask.

Also, please don't top post :).


Alex