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Re: [Qemu-ppc] [PATCH] openpic: Added BRR1 register
From: |
Alexander Graf |
Subject: |
Re: [Qemu-ppc] [PATCH] openpic: Added BRR1 register |
Date: |
Mon, 16 Jul 2012 18:26:56 +0200 |
On 16.07.2012, at 18:21, Bhushan Bharat-R65777 <address@hidden> wrote:
>
>
>> -----Original Message-----
>> From: Alexander Graf [mailto:address@hidden
>> Sent: Monday, July 16, 2012 8:25 PM
>> To: Bhushan Bharat-R65777
>> Cc: address@hidden; address@hidden; Bhushan Bharat-R65777
>> Subject: Re: [PATCH] openpic: Added BRR1 register
>>
>> On 07/12/2012 01:07 PM, Bharat Bhushan wrote:
>>> Linux mpic driver uses (changes may be in pipeline to get upstreamed
>>> soon) BRR1. This patch adds the support to emulate readonly BRR1.
>>>
>>> Signed-off-by: Bharat Bhushan<address@hidden>
>>> ---
>>> hw/openpic.c | 6 ++++++
>>> 1 files changed, 6 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/hw/openpic.c b/hw/openpic.c index 58ef871..244155b 100644
>>> --- a/hw/openpic.c
>>> +++ b/hw/openpic.c
>>> @@ -595,6 +595,8 @@ static void openpic_gbl_write (void *opaque,
>> target_phys_addr_t addr, uint32_t v
>>> if (addr& 0xF)
>>> return;
>>> switch (addr) {
>>> + case 0x00: /* BRR1 Readonly */
>>> + break;
>>> case 0x40:
>>> case 0x50:
>>> case 0x60:
>>> @@ -671,6 +673,7 @@ static uint32_t openpic_gbl_read (void *opaque,
>> target_phys_addr_t addr)
>>> case 0x1090: /* PINT */
>>> retval = 0x00000000;
>>> break;
>>> + case 0x00:
>>
>> Add a comment saying what register this is. We really should be using
>> #define's
>> here, but it would be even worse to have it converted only half-way, so just
>> stick with the comment for now.
>
> Ok, I have added on write but forgot here.
>
>>
>>> case 0x40:
>>> case 0x50:
>>> case 0x60:
>>> @@ -893,6 +896,9 @@ static uint32_t openpic_cpu_read_internal(void *opaque,
>> target_phys_addr_t addr,
>>> dst =&opp->dst[idx];
>>> addr&= 0xFF0;
>>> switch (addr) {
>>> + case 0x00: /* BRR1 */
>>> + retval = 0x00400200;
>>
>> Please unmagicify this one :)
>
> /* BRR1 ( Block revision register ) */
>
> #define IPID 0x00400000 /* IP-block ID */
> #define IPMJ 0x00000200 /* IP major number */
> #define IPMN 0x00000200 /* IP minor number */
>
> case 0x00: /* BRR1 */
> retval = IPID | IPMJ | IPMN;
>
> Dose this look ok?
Yup :)
Alex
>
> Thanks
> -Bharat
>
>>
>>
>> Alex
>>
>>> + break;
>>> case 0x80: /* PCTP */
>>> retval = dst->pctp;
>>> break;
>>
>
>
> --
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- [Qemu-ppc] [PATCH] openpic: Added BRR1 register, Bharat Bhushan, 2012/07/12
- Re: [Qemu-ppc] [PATCH] openpic: Added BRR1 register, Alexander Graf, 2012/07/16
- Re: [Qemu-ppc] [PATCH] openpic: Added BRR1 register, Bhushan Bharat-R65777, 2012/07/16
- Re: [Qemu-ppc] [PATCH] openpic: Added BRR1 register,
Alexander Graf <=
- Re: [Qemu-ppc] [PATCH] openpic: Added BRR1 register, Scott Wood, 2012/07/16
- Re: [Qemu-ppc] [PATCH] openpic: Added BRR1 register, Bhushan Bharat-R65777, 2012/07/16
- Re: [Qemu-ppc] [PATCH] openpic: Added BRR1 register, Scott Wood, 2012/07/16
- Re: [Qemu-ppc] [PATCH] openpic: Added BRR1 register, Yoder Stuart-B08248, 2012/07/16
- Re: [Qemu-ppc] [PATCH] openpic: Added BRR1 register, Scott Wood, 2012/07/16
- Re: [Qemu-ppc] [PATCH] openpic: Added BRR1 register, Alexander Graf, 2012/07/16
- Re: [Qemu-ppc] [PATCH] openpic: Added BRR1 register, Scott Wood, 2012/07/16
- Re: [Qemu-ppc] [PATCH] openpic: Added BRR1 register, Yin Olivia-R63875, 2012/07/16