Re: [Qemu-discuss] 答复: Re: Output many return values of some instruction

[Peter Maydell]

On 1 December 2014 at 10:25,  <address@hidden> wrote:
>     Firstly, I tell you about my instruction -- Getsec (opcode is 0f 37), it 
> is about the x86 arch safer mode . I want to emulate it by QEMU.
>     Then, the function of Getsec is so complicated. There are
> many jmp or je/z opcode in this function. According to QEMU
> spirit, if jump instruction occurs, it should be jump to next
> TB. But for me, this is an atomic instruction.

You seem to be confused between:
 * conditions in the Intel architecture manual describing
   how the function performs
 * conditional jumps in x86 guest code
 * conditional jumps in TCG intermediate code
 * jumps between translation blocks

These are not all the same thing.

> I cannot separate this function to portions. And It is
> complicated to modify the main sequence of QEMU. If no jump
> in my function, I think it is simple to add some function in
> Getsec (in disas_insn()).

Complicated functions can be implemented by calling out
to C code in the frontend at runtime, as I suggested.
Yes, some instructions are complicated -- in the end
they all come down to modifying the state of the emulated
CPU, and you can do this always by using TCG ops or by
calling frontend functions.

You don't need to worry about atomicity -- TCG only runs
one guest CPU at a time, so any sequence of TCG ops within
one TCG TB will always execute atomically.

That said, given the "leaf" structure intel have used for
the getsec instruction, you're probably best off just
calling a helper function and figuring out which leaf op
this is at runtime.

>     Lastly, do our QEMU have a schedule for Getsec implemention?

No, we don't.

-- PMM