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[PULL 17/49] target/riscv: add riscv_cpu_accelerator_compatible()
From: |
Alistair Francis |
Subject: |
[PULL 17/49] target/riscv: add riscv_cpu_accelerator_compatible() |
Date: |
Tue, 7 Nov 2023 12:29:13 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Add an API to check if a given CPU is compatible with the current
accelerator.
This will allow query-cpu-model-expansion to work properly in conditions
where QEMU supports both accelerators (TCG and KVM), QEMU is then
launched using TCG, and the API requests information about a KVM only
CPU (e.g. 'host' CPU).
KVM doesn't have such restrictions and, at least in theory, all CPUs
models should work with KVM. We will revisit this API in case we decide
to restrict the amount of KVM CPUs we support.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231018195638.211151-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 +
target/riscv/tcg/tcg-cpu.h | 1 +
target/riscv/cpu.c | 9 +++++++++
target/riscv/tcg/tcg-cpu.c | 7 ++++++-
4 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 8c9ec59d82..8efc4d83ec 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -758,6 +758,7 @@ char *riscv_cpu_get_name(RISCVCPU *cpu);
void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
void riscv_add_satp_mode_properties(Object *obj);
+bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu);
/* CSR function table */
extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
index aa00fbc253..f7b32417f8 100644
--- a/target/riscv/tcg/tcg-cpu.h
+++ b/target/riscv/tcg/tcg-cpu.h
@@ -24,5 +24,6 @@
void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
+bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
#endif
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 02db0834dd..8e0abe33d3 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1063,6 +1063,15 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
mcc->parent_realize(dev, errp);
}
+bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu)
+{
+ if (tcg_enabled()) {
+ return riscv_cpu_tcg_compatible(cpu);
+ }
+
+ return true;
+}
+
#ifndef CONFIG_USER_ONLY
static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 21a46f2a0e..6771617226 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -581,6 +581,11 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error
**errp)
}
}
+bool riscv_cpu_tcg_compatible(RISCVCPU *cpu)
+{
+ return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL;
+}
+
static bool riscv_cpu_is_generic(Object *cpu_obj)
{
return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
@@ -598,7 +603,7 @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp)
RISCVCPU *cpu = RISCV_CPU(cs);
Error *local_err = NULL;
- if (object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) {
+ if (!riscv_cpu_tcg_compatible(cpu)) {
g_autofree char *name = riscv_cpu_get_name(cpu);
error_setg(errp, "'%s' CPU is not compatible with TCG acceleration",
name);
--
2.41.0
- [PULL 07/49] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled, (continued)
- [PULL 07/49] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled, Alistair Francis, 2023/11/06
- [PULL 08/49] target/riscv: Split interrupt logic from riscv_cpu_update_mip., Alistair Francis, 2023/11/06
- [PULL 09/49] target/riscv: Add M-mode virtual interrupt and IRQ filtering support., Alistair Francis, 2023/11/06
- [PULL 10/49] target/riscv: Add HS-mode virtual interrupt and IRQ filtering support., Alistair Francis, 2023/11/06
- [PULL 12/49] docs/system/riscv: update 'virt' machine core limit, Alistair Francis, 2023/11/06
- [PULL 13/49] target/riscv/kvm/kvm-cpu.c: add missing property getters(), Alistair Francis, 2023/11/06
- [PULL 11/49] linux-user/riscv: change default cpu to 'max', Alistair Francis, 2023/11/06
- [PULL 14/49] qapi,risc-v: add query-cpu-model-expansion, Alistair Francis, 2023/11/06
- [PULL 16/49] target/riscv: handle custom props in qmp_query_cpu_model_expansion, Alistair Francis, 2023/11/06
- [PULL 15/49] target/riscv/tcg: add tcg_cpu_finalize_features(), Alistair Francis, 2023/11/06
- [PULL 17/49] target/riscv: add riscv_cpu_accelerator_compatible(),
Alistair Francis <=
- [PULL 20/49] target/riscv: pmp: Clear pmp/smepmp bits on reset, Alistair Francis, 2023/11/06
- [PULL 21/49] target/riscv: pmp: Ignore writes when RW=01, Alistair Francis, 2023/11/06
- [PULL 18/49] target/riscv/riscv-qmp-cmds.c: check CPU accel in query-cpu-model-expansion, Alistair Francis, 2023/11/06
- [PULL 22/49] target/riscv: add zicntr extension flag for TCG, Alistair Francis, 2023/11/06
- [PULL 19/49] Add epmp to extensions list and rename it to smepmp, Alistair Francis, 2023/11/06
- [PULL 23/49] target/riscv/kvm: add zicntr reg, Alistair Francis, 2023/11/06
- [PULL 24/49] target/riscv: add zihpm extension flag for TCG, Alistair Francis, 2023/11/06
- [PULL 25/49] target/riscv/kvm: add zihpm reg, Alistair Francis, 2023/11/06
- [PULL 26/49] target/riscv/kvm: add zicsr, zifencei, zba, zbs, svnapot, Alistair Francis, 2023/11/06
- [PULL 27/49] target/riscv: correct csr_ops[CSR_MSECCFG], Alistair Francis, 2023/11/06