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[PULL v2 41/78] hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS
From: |
Michael S. Tsirkin |
Subject: |
[PULL v2 41/78] hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS |
Date: |
Thu, 19 Oct 2023 14:22:59 -0400 |
From: Bernhard Beschow <shentey@gmail.com>
PIIX_NUM_PIC_IRQS is assumed to be the same as ISA_NUM_IRQS, otherwise
inconsistencies can occur.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-5-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/southbridge/piix.h | 5 ++---
hw/isa/piix3.c | 8 ++++----
2 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index 278171752f..2317bb7974 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -27,7 +27,6 @@
*/
#define PIIX_RCR_IOPORT 0xcf9
-#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
struct PIIXState {
@@ -39,10 +38,10 @@ struct PIIXState {
* So one PIC level is tracked by PIIX_NUM_PIRQS bits.
*
* PIRQ is mapped to PIC pins, we track it by
- * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
+ * PIIX_NUM_PIRQS * ISA_NUM_IRQS = 64 bits with
* pic_irq * PIIX_NUM_PIRQS + pirq
*/
-#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
+#if ISA_NUM_IRQS * PIIX_NUM_PIRQS > 64
#error "unable to encode pic state in 64bit in pic_levels."
#endif
uint64_t pic_levels;
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index 117024e450..7240c91440 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -48,7 +48,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix3,
int pirq, int level)
uint64_t mask;
pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
- if (pic_irq >= PIIX_NUM_PIC_IRQS) {
+ if (pic_irq >= ISA_NUM_IRQS) {
return;
}
@@ -62,7 +62,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq,
int level)
int pic_irq;
pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
- if (pic_irq >= PIIX_NUM_PIC_IRQS) {
+ if (pic_irq >= ISA_NUM_IRQS) {
return;
}
@@ -83,7 +83,7 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque,
int pin)
int irq = piix3->dev.config[PIIX_PIRQCA + pin];
PCIINTxRoute route;
- if (irq < PIIX_NUM_PIC_IRQS) {
+ if (irq < ISA_NUM_IRQS) {
route.mode = PCI_INTX_ENABLED;
route.irq = irq;
} else {
@@ -115,7 +115,7 @@ static void piix3_write_config(PCIDevice *dev,
pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
piix3_update_irq_levels(piix3);
- for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
+ for (pic_irq = 0; pic_irq < ISA_NUM_IRQS; pic_irq++) {
piix3_set_irq_pic(piix3, pic_irq);
}
}
--
MST
- [PULL v2 27/78] vhost-user: flatten "enforce_reply" into "vhost_user_write_sync", (continued)
- [PULL v2 27/78] vhost-user: flatten "enforce_reply" into "vhost_user_write_sync", Michael S. Tsirkin, 2023/10/19
- [PULL v2 45/78] hw/i386/pc_q35: Wire ICH9 LPC function's interrupts before its realize(), Michael S. Tsirkin, 2023/10/19
- [PULL v2 48/78] hw/isa/piix3: Create IDE controller in host device, Michael S. Tsirkin, 2023/10/19
- [PULL v2 52/78] hw/isa/piix4: Remove unused inbound ISA interrupt lines, Michael S. Tsirkin, 2023/10/19
- [PULL v2 30/78] vhost-user: call VHOST_USER_SET_VRING_ENABLE synchronously, Michael S. Tsirkin, 2023/10/19
- [PULL v2 36/78] timer/i8254: Fix one shot PIT mode, Michael S. Tsirkin, 2023/10/19
- [PULL v2 31/78] memory: initialize 'fv' in MemoryRegionCache to make Coverity happy, Michael S. Tsirkin, 2023/10/19
- [PULL v2 50/78] hw/isa/piix3: Create power management controller in host device, Michael S. Tsirkin, 2023/10/19
- [PULL v2 34/78] virtio: call ->vhost_reset_device() during reset, Michael S. Tsirkin, 2023/10/19
- [PULL v2 38/78] hw/i386/pc: Merge two if statements into one, Michael S. Tsirkin, 2023/10/19
- [PULL v2 41/78] hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS,
Michael S. Tsirkin <=
- [PULL v2 22/78] tests: bios-tables-test: Add test for smbios type4 thread count2, Michael S. Tsirkin, 2023/10/19
- [PULL v2 26/78] vhost-user: factor out "vhost_user_write_sync", Michael S. Tsirkin, 2023/10/19
- [PULL v2 32/78] vhost-user: do not send RESET_OWNER on device reset, Michael S. Tsirkin, 2023/10/19
- [PULL v2 40/78] hw/i386/pc_piix: Assign PIIX3's ISA interrupts before its realize(), Michael S. Tsirkin, 2023/10/19
- [PULL v2 43/78] hw/i386/pc_piix: Remove redundant "piix3" variable, Michael S. Tsirkin, 2023/10/19
- [PULL v2 42/78] hw/i386/pc_piix: Wire PIIX3's ISA interrupts by new "isa-irqs" property, Michael S. Tsirkin, 2023/10/19
- [PULL v2 46/78] hw/isa/piix3: Wire PIC IRQs to ISA bus in host device, Michael S. Tsirkin, 2023/10/19
- [PULL v2 51/78] hw/isa/piix3: Drop the "3" from PIIX base class name, Michael S. Tsirkin, 2023/10/19
- [PULL v2 54/78] hw/isa/piix4: Rename reset control operations to match PIIX3, Michael S. Tsirkin, 2023/10/19
- [PULL v2 56/78] hw/isa/piix3: Merge hw/isa/piix4.c, Michael S. Tsirkin, 2023/10/19