[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 01/12] target/arm: Use extract2 for EXTR
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 01/12] target/arm: Use extract2 for EXTR |
Date: |
Thu, 23 May 2019 15:23:46 +0100 |
From: Richard Henderson <address@hidden>
This is, after all, how we implement extract2 in tcg/aarch64.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate-a64.c | 38 ++++++++++++++++++++------------------
1 file changed, 20 insertions(+), 18 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index b7c5a928b4a..2b135b938ce 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -4114,25 +4114,27 @@ static void disas_extract(DisasContext *s, uint32_t
insn)
} else {
tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm));
}
- } else if (rm == rn) { /* ROR */
- tcg_rm = cpu_reg(s, rm);
- if (sf) {
- tcg_gen_rotri_i64(tcg_rd, tcg_rm, imm);
- } else {
- TCGv_i32 tmp = tcg_temp_new_i32();
- tcg_gen_extrl_i64_i32(tmp, tcg_rm);
- tcg_gen_rotri_i32(tmp, tmp, imm);
- tcg_gen_extu_i32_i64(tcg_rd, tmp);
- tcg_temp_free_i32(tmp);
- }
} else {
- tcg_rm = read_cpu_reg(s, rm, sf);
- tcg_rn = read_cpu_reg(s, rn, sf);
- tcg_gen_shri_i64(tcg_rm, tcg_rm, imm);
- tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm);
- tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn);
- if (!sf) {
- tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
+ tcg_rm = cpu_reg(s, rm);
+ tcg_rn = cpu_reg(s, rn);
+
+ if (sf) {
+ /* Specialization to ROR happens in EXTRACT2. */
+ tcg_gen_extract2_i64(tcg_rd, tcg_rm, tcg_rn, imm);
+ } else {
+ TCGv_i32 t0 = tcg_temp_new_i32();
+
+ tcg_gen_extrl_i64_i32(t0, tcg_rm);
+ if (rm == rn) {
+ tcg_gen_rotri_i32(t0, t0, imm);
+ } else {
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ tcg_gen_extrl_i64_i32(t1, tcg_rn);
+ tcg_gen_extract2_i32(t0, t0, t1, imm);
+ tcg_temp_free_i32(t1);
+ }
+ tcg_gen_extu_i32_i64(tcg_rd, t0);
+ tcg_temp_free_i32(t0);
}
}
}
--
2.20.1
- [Qemu-devel] [PULL 00/12] target-arm queue, Peter Maydell, 2019/05/23
- [Qemu-devel] [PULL 01/12] target/arm: Use extract2 for EXTR,
Peter Maydell <=
- [Qemu-devel] [PULL 02/12] target/arm: Simplify BFXIL expansion, Peter Maydell, 2019/05/23
- [Qemu-devel] [PULL 03/12] target/arm: Fix vector operation segfault, Peter Maydell, 2019/05/23
- [Qemu-devel] [PULL 04/12] arm: Move system_clock_scale to armv7m_systick.h, Peter Maydell, 2019/05/23
- [Qemu-devel] [PULL 05/12] arm: Remove unnecessary includes of hw/arm/arm.h, Peter Maydell, 2019/05/23
- [Qemu-devel] [PULL 11/12] hw/arm/exynos4210: Add DMA support for the Exynos4210, Peter Maydell, 2019/05/23
- [Qemu-devel] [PULL 07/12] hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}, Peter Maydell, 2019/05/23
- [Qemu-devel] [PULL 12/12] hw/arm/exynos4210: QOM'ify the Exynos4210 SoC, Peter Maydell, 2019/05/23
- [Qemu-devel] [PULL 08/12] hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3, Peter Maydell, 2019/05/23
- [Qemu-devel] [PULL 10/12] hw/arm/exynos4: Use the IEC binary prefix definitions, Peter Maydell, 2019/05/23
- [Qemu-devel] [PULL 09/12] hw/arm/exynos4: Remove unuseful debug code, Peter Maydell, 2019/05/23