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[Qemu-devel] [PATCH v15 02/12] hw/registerfields.h: Add 8bit and 16bit r
From: |
Yoshinori Sato |
Subject: |
[Qemu-devel] [PATCH v15 02/12] hw/registerfields.h: Add 8bit and 16bit register macros. |
Date: |
Wed, 22 May 2019 23:29:46 +0900 |
Some RX peripheral using 8bit and 16bit registers.
Added 8bit and 16bit APIs.
Signed-off-by: Yoshinori Sato <address@hidden>
---
include/hw/registerfields.h | 30 +++++++++++++++++++++++++++++-
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h
index 2659a58737..8573bdd7db 100644
--- a/include/hw/registerfields.h
+++ b/include/hw/registerfields.h
@@ -13,11 +13,17 @@
#include "qemu/bitops.h"
-/* Define constants for a 32 bit register */
+/* Define constants for a 8, 16 and 32 bit register */
/* This macro will define A_FOO, for the byte address of a register
* as well as R_FOO for the uint32_t[] register number (A_FOO / 4).
*/
+#define REG8(reg, addr) \
+ enum { A_ ## reg = (addr) }; \
+ enum { R_ ## reg = (addr) };
+#define REG16(reg, addr) \
+ enum { A_ ## reg = (addr) }; \
+ enum { R_ ## reg = (addr) / 2 };
#define REG32(reg, addr) \
enum { A_ ## reg = (addr) }; \
enum { R_ ## reg = (addr) / 4 };
@@ -34,6 +40,12 @@
MAKE_64BIT_MASK(shift, length)};
/* Extract a field from a register */
+#define FIELD_EX8(storage, reg, field) \
+ extract8((storage), R_ ## reg ## _ ## field ## _SHIFT, \
+ R_ ## reg ## _ ## field ## _LENGTH)
+#define FIELD_EX16(storage, reg, field) \
+ extract16((storage), R_ ## reg ## _ ## field ## _SHIFT, \
+ R_ ## reg ## _ ## field ## _LENGTH)
#define FIELD_EX32(storage, reg, field) \
extract32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
R_ ## reg ## _ ## field ## _LENGTH)
@@ -49,6 +61,22 @@
* Assigning values larger then the target field will result in
* compilation warnings.
*/
+#define FIELD_DP8(storage, reg, field, val) ({ \
+ struct { \
+ unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \
+ } v = { .v = val }; \
+ uint8_t d; \
+ d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
+ R_ ## reg ## _ ## field ## _LENGTH, v.v); \
+ d; })
+#define FIELD_DP16(storage, reg, field, val) ({ \
+ struct { \
+ unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \
+ } v = { .v = val }; \
+ uint16_t d; \
+ d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
+ R_ ## reg ## _ ## field ## _LENGTH, v.v); \
+ d; })
#define FIELD_DP32(storage, reg, field, val) ({ \
struct { \
unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \
--
2.11.0
- [Qemu-devel] [PATCH v15 00/12] Add RX archtecture support, Yoshinori Sato, 2019/05/22
- [Qemu-devel] [PATCH v15 12/12] MAINTAINERS: Add RX, Yoshinori Sato, 2019/05/22
- [Qemu-devel] [PATCH v15 01/12] qemu/bitops.h: Add extract8 and extract16, Yoshinori Sato, 2019/05/22
- [Qemu-devel] [PATCH v15 02/12] hw/registerfields.h: Add 8bit and 16bit register macros.,
Yoshinori Sato <=
- [Qemu-devel] [PATCH v15 11/12] Add rx-softmmu, Yoshinori Sato, 2019/05/22
- [Qemu-devel] [PATCH v15 09/12] hw/char: RX62N serial communication interface (SCI), Yoshinori Sato, 2019/05/22
- [Qemu-devel] [PATCH v15 10/12] hw/rx: RX Target hardware definition, Yoshinori Sato, 2019/05/22
- [Qemu-devel] [PATCH v15 08/12] hw/timer: RX62N internal timer modules, Yoshinori Sato, 2019/05/22
- [Qemu-devel] [PATCH v15 05/12] target/rx: CPU definition, Yoshinori Sato, 2019/05/22
- [Qemu-devel] [PATCH v15 07/12] hw/intc: RX62N interrupt controller (ICUa), Yoshinori Sato, 2019/05/22
- [Qemu-devel] [PATCH v15 04/12] target/rx: TCG helper, Yoshinori Sato, 2019/05/22
- [Qemu-devel] [PATCH v15 06/12] target/rx: RX disassembler, Yoshinori Sato, 2019/05/22
- [Qemu-devel] [PATCH v15 03/12] target/rx: TCG translation, Yoshinori Sato, 2019/05/22
- Re: [Qemu-devel] [PATCH v15 00/12] Add RX archtecture support, Philippe Mathieu-Daudé, 2019/05/22