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Re: [Qemu-devel] [PATCH] Implement Fraction Rounded bit in FPSCR for Pow
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From: |
Richard Henderson |
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Subject: |
Re: [Qemu-devel] [PATCH] Implement Fraction Rounded bit in FPSCR for PowerPC |
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Date: |
Tue, 21 May 2019 23:30:31 -0400 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 |
On 5/21/19 8:06 PM, John Arbuckle wrote:
> Implement the PowerPC floating point status and control register flag
> Fraction Rounded.
>
> Signed-off-by: John Arbuckle <address@hidden>
> ---
> fpu/softfloat.c | 15 ++++++++++++---
> include/fpu/softfloat-types.h | 1 +
> target/ppc/fpu_helper.c | 4 ++++
> 3 files changed, 17 insertions(+), 3 deletions(-)
Please split the target/ppc part away from the softfloat part.
Also, we should note that there are more places within softfloat that need to
be adjusted so that float_float_rounded is fully supported.
r~