[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 6/9] target/xtensa: implement DIWBUI.P opcode
From: |
Max Filippov |
Subject: |
[Qemu-devel] [PATCH 6/9] target/xtensa: implement DIWBUI.P opcode |
Date: |
Tue, 14 May 2019 13:44:44 -0700 |
This is a recent addition to the set of data cache opcodes.
Signed-off-by: Max Filippov <address@hidden>
---
target/xtensa/cpu.h | 1 +
target/xtensa/overlay_tool.h | 1 +
target/xtensa/translate.c | 10 ++++++++++
3 files changed, 12 insertions(+)
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index d6e6bf6ca183..ba4ef2b6a729 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -466,6 +466,7 @@ struct XtensaConfig {
unsigned icache_ways;
unsigned dcache_ways;
+ unsigned dcache_line_bytes;
uint32_t memctl_mask;
XtensaMemory instrom;
diff --git a/target/xtensa/overlay_tool.h b/target/xtensa/overlay_tool.h
index b61c92539861..4925b21f0edf 100644
--- a/target/xtensa/overlay_tool.h
+++ b/target/xtensa/overlay_tool.h
@@ -425,6 +425,7 @@
#define CACHE_SECTION \
.icache_ways = XCHAL_ICACHE_WAYS, \
.dcache_ways = XCHAL_DCACHE_WAYS, \
+ .dcache_line_bytes = XCHAL_DCACHE_LINESIZE, \
.memctl_mask = \
(XCHAL_ICACHE_SIZE ? MEMCTL_IUSEWAYS_MASK : 0) | \
(XCHAL_DCACHE_SIZE ? \
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 782f2ec62099..24eb70d619d5 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -1620,6 +1620,12 @@ static void translate_depbits(DisasContext *dc, const
OpcodeArg arg[],
arg[2].imm, arg[3].imm);
}
+static void translate_diwbuip(DisasContext *dc, const OpcodeArg arg[],
+ const uint32_t par[])
+{
+ tcg_gen_addi_i32(arg[0].out, arg[0].in, dc->config->dcache_line_bytes);
+}
+
static bool test_ill_entry(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
@@ -3098,6 +3104,10 @@ static const XtensaOpcodeOps core_ops[] = {
.translate = translate_nop,
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
+ .name = "diwbui.p",
+ .translate = translate_diwbuip,
+ .op_flags = XTENSA_OP_PRIVILEGED,
+ }, {
.name = "dpfl",
.translate = translate_dcache,
.op_flags = XTENSA_OP_PRIVILEGED,
--
2.11.0
- [Qemu-devel] [PATCH 0/9] target/xtensa: implement options for modern cores, Max Filippov, 2019/05/14
- [Qemu-devel] [PATCH 3/9] target/xtensa: define IDMA and gather/scatter IRQ types, Max Filippov, 2019/05/14
- [Qemu-devel] [PATCH 8/9] target/xtensa: update list of exception causes, Max Filippov, 2019/05/14
- [Qemu-devel] [PATCH 7/9] target/xtensa: implement block prefetch option opcodes, Max Filippov, 2019/05/14
- [Qemu-devel] [PATCH 9/9] target/xtensa: implement exclusive access option, Max Filippov, 2019/05/14
- [Qemu-devel] [PATCH 6/9] target/xtensa: implement DIWBUI.P opcode,
Max Filippov <=
- [Qemu-devel] [PATCH 4/9] target/xtensa: add parity/ECC option SRs, Max Filippov, 2019/05/14
- [Qemu-devel] [PATCH 5/9] target/xtensa: implement MPU option, Max Filippov, 2019/05/14
- [Qemu-devel] [PATCH 2/9] target/xtensa: make internal MMU functions static, Max Filippov, 2019/05/14
- [Qemu-devel] [PATCH 1/9] target/xtensa: get rid of centralized SR properties, Max Filippov, 2019/05/14