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Re: [Qemu-devel] [PATCH v2 07/29] tcg: Support cross-class moves without
From: |
Alex Bennée |
Subject: |
Re: [Qemu-devel] [PATCH v2 07/29] tcg: Support cross-class moves without instruction support |
Date: |
Wed, 01 May 2019 18:34:02 +0100 |
User-agent: |
mu4e 1.3.1; emacs 26.1 |
Richard Henderson <address@hidden> writes:
> PowerPC Altivec does not support direct moves between vector registers
> and general registers. So when tcg_out_mov fails, we can use the
> backing memory for the temporary to perform the move.
I couldn't see where tcg_out_mov fails in this way for ppc, it is still
abort or pass:
static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
{
tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
if (ret != arg) {
tcg_out32(s, OR | SAB(arg, ret, arg));
}
return true;
}
did a patch get missed somewhere?
>
> Acked-by: David Hildenbrand <address@hidden>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
> tcg/tcg.c | 31 ++++++++++++++++++++++++++++---
> 1 file changed, 28 insertions(+), 3 deletions(-)
>
> diff --git a/tcg/tcg.c b/tcg/tcg.c
> index 8ed7cb8654..68d86361e2 100644
> --- a/tcg/tcg.c
> +++ b/tcg/tcg.c
> @@ -3368,7 +3368,20 @@ static void tcg_reg_alloc_mov(TCGContext *s, const
> TCGOp *op)
> ots->indirect_base);
> }
> if (!tcg_out_mov(s, otype, ots->reg, ts->reg)) {
> - abort();
> + /*
> + * Cross register class move not supported.
> + * Store the source register into the destination slot
> + * and leave the destination temp as TEMP_VAL_MEM.
> + */
> + assert(!ots->fixed_reg);
> + if (!ts->mem_allocated) {
> + temp_allocate_frame(s, ots);
> + }
> + tcg_out_st(s, ts->type, ts->reg,
> + ots->mem_base->reg, ots->mem_offset);
> + ots->mem_coherent = 1;
> + temp_free_or_dead(s, ots, -1);
> + return;
> }
> }
> ots->val_type = TEMP_VAL_REG;
> @@ -3470,7 +3483,13 @@ static void tcg_reg_alloc_op(TCGContext *s, const
> TCGOp *op)
> reg = tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs,
> o_preferred_regs, ts->indirect_base);
> if (!tcg_out_mov(s, ts->type, reg, ts->reg)) {
> - abort();
> + /*
> + * Cross register class move not supported. Sync the
> + * temp back to its slot and load from there.
> + */
> + temp_sync(s, ts, i_allocated_regs, 0, 0);
> + tcg_out_ld(s, ts->type, reg,
> + ts->mem_base->reg, ts->mem_offset);
> }
> }
> new_args[i] = reg;
> @@ -3631,7 +3650,13 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp
> *op)
> if (ts->reg != reg) {
> tcg_reg_free(s, reg, allocated_regs);
> if (!tcg_out_mov(s, ts->type, reg, ts->reg)) {
> - abort();
> + /*
> + * Cross register class move not supported. Sync the
> + * temp back to its slot and load from there.
> + */
> + temp_sync(s, ts, allocated_regs, 0, 0);
> + tcg_out_ld(s, ts->type, reg,
> + ts->mem_base->reg, ts->mem_offset);
> }
> }
> } else {
--
Alex Bennée
- Re: [Qemu-devel] [PATCH v2 04/29] tcg: Specify optional vector requirements with a list, (continued)
- [Qemu-devel] [PATCH v2 05/29] tcg: Assert fixed_reg is read-only, Richard Henderson, 2019/05/01
- [Qemu-devel] [PATCH v2 06/29] tcg: Return bool success from tcg_out_mov, Richard Henderson, 2019/05/01
- [Qemu-devel] [PATCH v2 08/29] tcg: Promote tcg_out_{dup, dupi}_vec to backend interface, Richard Henderson, 2019/05/01
- [Qemu-devel] [PATCH v2 07/29] tcg: Support cross-class moves without instruction support, Richard Henderson, 2019/05/01
- Re: [Qemu-devel] [PATCH v2 07/29] tcg: Support cross-class moves without instruction support,
Alex Bennée <=
- [Qemu-devel] [PATCH v2 09/29] tcg: Manually expand INDEX_op_dup_vec, Richard Henderson, 2019/05/01
- [Qemu-devel] [PATCH v2 10/29] tcg: Add tcg_out_dupm_vec to the backend interface, Richard Henderson, 2019/05/01
- [Qemu-devel] [PATCH v2 11/29] tcg/i386: Implement tcg_out_dupm_vec, Richard Henderson, 2019/05/01
- [Qemu-devel] [PATCH v2 13/29] tcg: Add INDEX_op_dup_mem_vec, Richard Henderson, 2019/05/01
- [Qemu-devel] [PATCH v2 16/29] tcg/aarch64: Support vector variable shift opcodes, Richard Henderson, 2019/05/01