qemu-devel
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-devel] [PATCH 2/2] target/riscv: Add checks for several RVC re


From: Palmer Dabbelt
Subject: Re: [Qemu-devel] [PATCH 2/2] target/riscv: Add checks for several RVC reserved operands
Date: Wed, 01 May 2019 10:21:29 -0700 (PDT)

On Thu, 25 Apr 2019 10:32:43 PDT (-0700), address@hidden wrote:
On 4/25/19 10:26 AM, Richard Henderson wrote:
 {
+  illegal         011 0  -----  00000 01 # c.addi16sp, RES nzimm=0
   addi            011 .  00010  ..... 01 @c_addi16sp
   lui             011 .  .....  ..... 01 @c_lui
 }

Bah.  I just realized the comment should be more like

  # c.addi16sp and c.lui, RES nzimm=0

Otherwise one is led to believe that rd=2 is missing
from the illegal pattern.

OK, I went ahead and squashed in that fix as well.




reply via email to

[Prev in Thread] Current Thread [Next in Thread]