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Re: [Qemu-devel] [PATCH RFC v4 01/12] target/rx: TCG translation
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH RFC v4 01/12] target/rx: TCG translation |
Date: |
Mon, 25 Mar 2019 08:50:53 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.5.1 |
On 3/25/19 2:38 AM, Yoshinori Sato wrote:
>>> +static bool trans_EMUL_mr(DisasContext *ctx, arg_EMUL_mr *a)
>>> +{
>>> + TCGv val, mem;
>>> + mem = tcg_temp_new();
>>> + val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs);
>>> + tcg_gen_muls2_i32(cpu_regs[a->rd], cpu_regs[a->rd + 1],
>>> + cpu_regs[a->rd], val);
>>
>> Both of these need to check for rd == 15 and return false.
>
> Specifying 15 for rd does not result in an invalid instruction.
> I made it to output a log.
Does the hardware wrap around and modify R0, then?
Whatever you do, you cannot allow the guest to read
beyond the end of the cpu_regs array.
>>> + gen_set_label(l1);
>>> + tcg_gen_movi_i32(cpu_psw_c, 0);
>>> + tcg_gen_movi_i32(cpu_psw_o, 0);
>>
>> Likewise.
>
> As this is a two-operand, rd does not change when the shift count is zero.
The insn may be two operand, but the arg structure is three operand. You have
written the entire rest of the function as if rd is relevant. If you add the
tcg_gen_mov_i32 you complete that illusion. However, there will be no mov
issued, because tcg_gen_mov_i32 checks for dest == src.
r~
- [Qemu-devel] [PATCH RFC v4 02/12] target/rx: TCG helper, (continued)
- [Qemu-devel] [PATCH RFC v4 07/12] hw/timer: RX62N internal timer modules, Yoshinori Sato, 2019/03/20
- [Qemu-devel] [PATCH RFC v4 08/12] hw/char: RX62N serical communication interface (SCI), Yoshinori Sato, 2019/03/20
- [Qemu-devel] [PATCH RFC v4 01/12] target/rx: TCG translation, Yoshinori Sato, 2019/03/20
- Re: [Qemu-devel] [PATCH RFC v4 01/12] target/rx: TCG translation, Richard Henderson, 2019/03/21
- Re: [Qemu-devel] [PATCH RFC v4 01/12] target/rx: TCG translation, Yoshinori Sato, 2019/03/25
- Re: [Qemu-devel] [PATCH RFC v4 01/12] target/rx: TCG translation,
Richard Henderson <=
- Re: [Qemu-devel] [PATCH RFC v4 01/12] target/rx: TCG translation, Yoshinori Sato, 2019/03/26
- Re: [Qemu-devel] [PATCH RFC v4 01/12] target/rx: TCG translation, Yoshinori Sato, 2019/03/27
Re: [Qemu-devel] [PATCH RFC v4 00/12] Add RX archtecture support, no-reply, 2019/03/20
[Qemu-devel] [PATCH RFC v5 00/12] Add RX archtecture support, Yoshinori Sato, 2019/03/25
- [Qemu-devel] [PATCH RFC v5 12/12] include/hw/regiserfields.h: Add 8bit and 16bit registers, Yoshinori Sato, 2019/03/25
- [Qemu-devel] [PATCH RFC v5 06/12] hw/intc: RX62N interrupt controller (ICUa), Yoshinori Sato, 2019/03/25
- [Qemu-devel] [PATCH RFC v5 05/12] target/rx: Miscellaneous files, Yoshinori Sato, 2019/03/25
- [Qemu-devel] [PATCH RFC v5 08/12] hw/char: RX62N serical communication interface (SCI), Yoshinori Sato, 2019/03/25
- [Qemu-devel] [PATCH RFC v5 09/12] hw/rx: RX Target hardware definition, Yoshinori Sato, 2019/03/25
- [Qemu-devel] [PATCH RFC v5 02/12] target/rx: TCG helper, Yoshinori Sato, 2019/03/25