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[Qemu-devel] [PULL 14/19] RISC-V: Convert trap debugging to trace events
From: |
Palmer Dabbelt |
Subject: |
[Qemu-devel] [PULL 14/19] RISC-V: Convert trap debugging to trace events |
Date: |
Tue, 19 Mar 2019 05:47:58 -0700 |
From: Michael Clark <address@hidden>
Cc: Palmer Dabbelt <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
Makefile.objs | 1 +
target/riscv/cpu_helper.c | 12 +++---------
target/riscv/trace-events | 2 ++
3 files changed, 6 insertions(+), 9 deletions(-)
create mode 100644 target/riscv/trace-events
diff --git a/Makefile.objs b/Makefile.objs
index 72debbf5c5de..cf065de5ed44 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -186,6 +186,7 @@ trace-events-subdirs += target/hppa
trace-events-subdirs += target/i386
trace-events-subdirs += target/mips
trace-events-subdirs += target/ppc
+trace-events-subdirs += target/riscv
trace-events-subdirs += target/s390x
trace-events-subdirs += target/sparc
trace-events-subdirs += ui
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index a02f4dad8c00..6d3fbc340165 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -22,8 +22,7 @@
#include "cpu.h"
#include "exec/exec-all.h"
#include "tcg-op.h"
-
-#define RISCV_DEBUG_INTERRUPT 0
+#include "trace.h"
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
{
@@ -493,13 +492,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
}
}
- if (RISCV_DEBUG_INTERRUPT) {
- qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld ": %s %s, "
- "epc 0x" TARGET_FMT_lx ": tval 0x" TARGET_FMT_lx "\n",
- env->mhartid, async ? "intr" : "trap",
- (async ? riscv_intr_names : riscv_excp_names)[cause],
- env->pc, tval);
- }
+ trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 16 ?
+ (async ? riscv_intr_names : riscv_excp_names)[cause] : "(unknown)");
if (env->priv <= PRV_S &&
cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
diff --git a/target/riscv/trace-events b/target/riscv/trace-events
new file mode 100644
index 000000000000..48af0373df6e
--- /dev/null
+++ b/target/riscv/trace-events
@@ -0,0 +1,2 @@
+# target/riscv/cpu_helper.c
+riscv_trap(uint64_t hartid, bool async, uint64_t cause, uint64_t epc, uint64_t
tval, const char *desc) "hart:%"PRId64", async:%d, cause:%"PRId64",
epc:0x%"PRIx64", tval:0x%"PRIx64", desc=%s"
--
2.19.2
- [Qemu-devel] [PULL] RISC-V Patches for 4.0-rc0, Part 2, Palmer Dabbelt, 2019/03/19
- [Qemu-devel] [PULL 10/19] elf: Add RISC-V PSABI ELF header defines, Palmer Dabbelt, 2019/03/19
- [Qemu-devel] [PULL 19/19] riscv: sifive_u: Correct UART0's IRQ in the device tree, Palmer Dabbelt, 2019/03/19
- [Qemu-devel] [PULL 18/19] riscv: sifive_uart: Generate TX interrupt, Palmer Dabbelt, 2019/03/19
- [Qemu-devel] [PULL 17/19] target/riscv: Remove unused struct, Palmer Dabbelt, 2019/03/19
- [Qemu-devel] [PULL 16/19] riscv: sifive_u: Allow up to 4 CPUs to be created, Palmer Dabbelt, 2019/03/19
- [Qemu-devel] [PULL 12/19] RISC-V: Change local interrupts from edge to level, Palmer Dabbelt, 2019/03/19
- [Qemu-devel] [PULL 15/19] RISC-V: Update load reservation comment in do_interrupt, Palmer Dabbelt, 2019/03/19
- [Qemu-devel] [PULL 14/19] RISC-V: Convert trap debugging to trace events,
Palmer Dabbelt <=
- [Qemu-devel] [PULL 13/19] RISC-V: Add support for vectored interrupts, Palmer Dabbelt, 2019/03/19
- [Qemu-devel] [PULL 11/19] RISC-V: linux-user support for RVE ABI, Palmer Dabbelt, 2019/03/19
- [Qemu-devel] [PULL 09/19] RISC-V: Remove unnecessary disassembler constraints, Palmer Dabbelt, 2019/03/19
- [Qemu-devel] [PULL 08/19] RISC-V: Allow interrupt controllers to claim interrupts, Palmer Dabbelt, 2019/03/19
- [Qemu-devel] [PULL 07/19] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC, Palmer Dabbelt, 2019/03/19
- [Qemu-devel] [PULL 05/19] RISC-V: Add hooks to use the gdb xml files., Palmer Dabbelt, 2019/03/19
- [Qemu-devel] [PULL 03/19] RISC-V: Fixes to CSR_* register macros., Palmer Dabbelt, 2019/03/19
- [Qemu-devel] [PULL 06/19] riscv: pmp: Log pmp access errors as guest errors, Palmer Dabbelt, 2019/03/19
- [Qemu-devel] [PULL 04/19] RISC-V: Add debug support for accessing CSRs., Palmer Dabbelt, 2019/03/19
- [Qemu-devel] [PULL 02/19] RISC-V: Add 64-bit gdb xml files., Palmer Dabbelt, 2019/03/19