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Re: [Qemu-devel] [PATCH] hw/arm/virt-acpi-build: Fix SMMUv3 GSIV values


From: Shannon Zhao
Subject: Re: [Qemu-devel] [PATCH] hw/arm/virt-acpi-build: Fix SMMUv3 GSIV values
Date: Wed, 13 Mar 2019 13:55:44 +0800
User-agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.5.3



On 2019/3/12 17:10, Eric Auger wrote:
The GSIV numbers of the SPI based interrupts is not correct as
ARM_SPI_BASE was not added to the irqmap[VIRT_SMMU] value. So
this may collide with VIRTIO_MMIO irq window.

Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>

---
  hw/arm/virt-acpi-build.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index d7e2e4885b..aa02d8d74e 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -405,7 +405,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, 
VirtMachineState *vms)
      its->identifiers[0] = 0; /* MADT translation_id */
if (vms->iommu == VIRT_IOMMU_SMMUV3) {
-        int irq =  vms->irqmap[VIRT_SMMU];
+        int irq =  vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE;
/* SMMUv3 node */
          smmu_offset = iort_node_offset + node_size;




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