Re: [Qemu-devel] [PATCH 01/27] ppc/xive: hardwire the Physical CAM line of the thread context

[David Gibson]

On Wed, Mar 06, 2019 at 09:50:06AM +0100, Cédric Le Goater wrote:
> By default on P9, the HW CAM line (23bits) is hardwired to :
> 
>       0x000||0b1||4Bit chip number||7Bit Thread number.
> 
> When the block group mode is enabled at the controller level (PowerNV),
> the CAM line is changed for CAM compares to :
> 
>       4Bit chip number||0x001||7Bit Thread number
> 
> This will require changes in xive_presenter_tctx_match() possibly.
> This is a lowlevel functionality of the HW controller and it is not
> strictly needed. Leave it for later.
> 
> Signed-off-by: Cédric Le Goater <address@hidden>

Applied to ppc-for-4.0, thanks.

> ---
>  hw/intc/xive.c | 31 ++++++++++++++++++++++++++++++-
>  1 file changed, 30 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/intc/xive.c b/hw/intc/xive.c
> index daa7badc8492..b21759c93856 100644
> --- a/hw/intc/xive.c
> +++ b/hw/intc/xive.c
> @@ -1112,6 +1112,30 @@ XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, 
> CPUState *cs)
>      return xrc->get_tctx(xrtr, cs);
>  }
>  
> +/*
> + * By default on P9, the HW CAM line (23bits) is hardwired to :
> + *
> + *   0x000||0b1||4Bit chip number||7Bit Thread number.
> + *
> + * When the block grouping is enabled, the CAM line is changed to :
> + *
> + *   4Bit chip number||0x001||7Bit Thread number.
> + */
> +static uint32_t hw_cam_line(uint8_t chip_id, uint8_t tid)
> +{
> +    return 1 << 11 | (chip_id & 0xf) << 7 | (tid & 0x7f);
> +}
> +
> +static bool xive_presenter_tctx_match_hw(XiveTCTX *tctx,
> +                                         uint8_t nvt_blk, uint32_t nvt_idx)
> +{
> +    CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env;
> +    uint32_t pir = env->spr_cb[SPR_PIR].default_value;
> +
> +    return hw_cam_line((pir >> 8) & 0xf, pir & 0x7f) ==
> +        hw_cam_line(nvt_blk, nvt_idx);
> +}
> +
>  /*
>   * The thread context register words are in big-endian format.
>   */
> @@ -1120,6 +1144,7 @@ static int xive_presenter_tctx_match(XiveTCTX *tctx, 
> uint8_t format,
>                                       bool cam_ignore, uint32_t logic_serv)
>  {
>      uint32_t cam = xive_nvt_cam_line(nvt_blk, nvt_idx);
> +    uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]);
>      uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]);
>      uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
>      uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]);
> @@ -1142,7 +1167,11 @@ static int xive_presenter_tctx_match(XiveTCTX *tctx, 
> uint8_t format,
>  
>          /* F=0 & i=0: Specific NVT notification */
>  
> -        /* TODO (PowerNV) : PHYS ring */
> +        /* PHYS ring */
> +        if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) &&
> +            xive_presenter_tctx_match_hw(tctx, nvt_blk, nvt_idx)) {
> +            return TM_QW3_HV_PHYS;
> +        }
>  
>          /* HV POOL ring */
>          if ((be32_to_cpu(qw2w2) & TM_QW2W2_VP) &&

-- 
David Gibson                    | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
                                | _way_ _around_!
http://www.ozlabs.org/~dgibson

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