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[Qemu-devel] [PULL 02/22] target/arm: Split out arm_sctlr
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 02/22] target/arm: Split out arm_sctlr |
Date: |
Tue, 5 Mar 2019 16:50:31 +0000 |
From: Richard Henderson <address@hidden>
Minimize the number of places that will need updating when
the virtual host extensions are added.
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu.h | 26 ++++++++++++++++----------
target/arm/helper.c | 8 ++------
2 files changed, 18 insertions(+), 16 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 36cd365efaf..67b06bfad09 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3042,11 +3042,20 @@ static inline bool arm_sctlr_b(CPUARMState *env)
(env->cp15.sctlr_el[1] & SCTLR_B) != 0;
}
+static inline uint64_t arm_sctlr(CPUARMState *env, int el)
+{
+ if (el == 0) {
+ /* FIXME: ARMv8.1-VHE S2 translation regime. */
+ return env->cp15.sctlr_el[1];
+ } else {
+ return env->cp15.sctlr_el[el];
+ }
+}
+
+
/* Return true if the processor is in big-endian mode. */
static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
{
- int cur_el;
-
/* In 32bit endianness is determined by looking at CPSR's E bit */
if (!is_a64(env)) {
return
@@ -3065,15 +3074,12 @@ static inline bool
arm_cpu_data_is_big_endian(CPUARMState *env)
arm_sctlr_b(env) ||
#endif
((env->uncached_cpsr & CPSR_E) ? 1 : 0);
+ } else {
+ int cur_el = arm_current_el(env);
+ uint64_t sctlr = arm_sctlr(env, cur_el);
+
+ return (sctlr & (cur_el ? SCTLR_EE : SCTLR_E0E)) != 0;
}
-
- cur_el = arm_current_el(env);
-
- if (cur_el == 0) {
- return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0;
- }
-
- return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0;
}
#include "exec/cpu-all.h"
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 1fa282a7fc1..49ff79a146b 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -12854,12 +12854,8 @@ void cpu_get_tb_cpu_state(CPUARMState *env,
target_ulong *pc,
flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len);
}
- if (current_el == 0) {
- /* FIXME: ARMv8.1-VHE S2 translation regime. */
- sctlr = env->cp15.sctlr_el[1];
- } else {
- sctlr = env->cp15.sctlr_el[current_el];
- }
+ sctlr = arm_sctlr(env, current_el);
+
if (cpu_isar_feature(aa64_pauth, cpu)) {
/*
* In order to save space in flags, we record only whether
--
2.20.1
- [Qemu-devel] [PULL 00/22] target-arm queue, Peter Maydell, 2019/03/05
- [Qemu-devel] [PULL 01/22] target/arm: Fix PC test for LDM (exception return), Peter Maydell, 2019/03/05
- [Qemu-devel] [PULL 02/22] target/arm: Split out arm_sctlr,
Peter Maydell <=
- [Qemu-devel] [PULL 03/22] target/arm: Implement ARMv8.0-SB, Peter Maydell, 2019/03/05
- [Qemu-devel] [PULL 06/22] target/arm: Add set/clear_pstate_bits, share gen_ss_advance, Peter Maydell, 2019/03/05
- [Qemu-devel] [PULL 05/22] target/arm: Split helper_msr_i_pstate into 3, Peter Maydell, 2019/03/05
- [Qemu-devel] [PULL 08/22] target/arm: Implement ARMv8.4-CondM, Peter Maydell, 2019/03/05
- [Qemu-devel] [PULL 04/22] target/arm: Implement ARMv8.0-PredInv, Peter Maydell, 2019/03/05
- [Qemu-devel] [PULL 09/22] target/arm: Implement ARMv8.5-CondM, Peter Maydell, 2019/03/05
- [Qemu-devel] [PULL 11/22] target/arm: Implement ARMv8.5-FRINT, Peter Maydell, 2019/03/05
- [Qemu-devel] [PULL 07/22] target/arm: Rearrange disas_data_proc_reg, Peter Maydell, 2019/03/05
- [Qemu-devel] [PULL 10/22] target/arm: Restructure handle_fp_1src_{single, double}, Peter Maydell, 2019/03/05
- [Qemu-devel] [PULL 12/22] hw/arm/boot: introduce fdt_add_memory_node helper, Peter Maydell, 2019/03/05