[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH v7 02/14] disas: nanoMIPS: Add graphical descrip
|
From: |
Philippe Mathieu-Daudé |
|
Subject: |
Re: [Qemu-devel] [PATCH v7 02/14] disas: nanoMIPS: Add graphical description of pool organization |
|
Date: |
Tue, 5 Mar 2019 15:07:04 +0100 |
|
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.5.1 |
On 3/5/19 1:39 PM, Aleksandar Markovic wrote:
>> From: Philippe Mathieu-Daudé <address@hidden>
>> Subject: Re: [Qemu-devel] [PATCH v7 02/14] disas: nanoMIPS: Add graphical
>> description of > pool organization
>>
>> On 3/4/19 10:08 PM, Aleksandar Markovic wrote:
>>> From: Aleksandar Markovic <address@hidden>
>>>
>>> Add graphical description of nanoMIPS instruction pool organization.
>>>
>>> Signed-off-by: Aleksandar Markovic <address@hidden>
>>> ---
>>> disas/nanomips.cpp | 102
>>> +++++++++++++++++++++++++++++++++++++++++++++++++++++
>>> 1 file changed, 102 insertions(+)
>>>
>>> diff --git a/disas/nanomips.cpp b/disas/nanomips.cpp
>>> index 10f6d96..9b44208 100644
>>> --- a/disas/nanomips.cpp
>>> +++ b/disas/nanomips.cpp
>>> @@ -16592,6 +16592,108 @@ std::string NMD::YIELD(uint64 instruction)
>>>
>>>
>>>
>>> +/*
>>> + * nanoMIPS instruction pool organization
>>> + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>>> + *
>>> + *
>>> + * ┌─ P.ADDIU ─── P.RI ─── P.SYSCALL
>>> + * │
>>> + * │ ┌─ P.TRAP
>>> + * │ │
>>> + * │ ┌─ _POOL32A0_0 ─┼─ P.CMOVE
>>> + * │ │ │
>>> + * │ │ └─ P.SLTU
>>> + * │ ┌─ _POOL32A0 ─┤
>>> + * │ │ │
>>> + * │ │ │
>>> + * │ │ └─ _POOL32A0_1 ─── CRC32
>>> + * │ │
>>> + * ├─ P32A ─┤
>>> + * │ │ ┌─ PP.LSX
>>> + * │ │ ┌─ P.LSX ─────┤
>>> + * │ │ │ └─ PP.LSXS
>>> + * │ └─ _POOL32A7 ─┤
>>> + * │ │ ┌─ POOL32Axf_4
>>> + * │ └─ POOL32Axf ─┤
>>> + * │ └─ POOL32Axf_5
>>> + * │
>>> + * ├─ PBAL
>>> + * │
>>> + * ├─ P.GP.W ┌─ PP.LSX
>>> + * ┌─ P32 ─┤ │
>>> + * │ ├─ P.GP.BH ─┴─ PP.LSXS
>>> + * │ │
>>> + * │ ├─ P.J ─────── PP.BALRSC
>>> + * │ │
>>> + * │ ├─ P48I
>>> + * │ │ ┌─ P.SR
>>> + * │ │ │
>>> + * │ │ ├─ P.SHIFT
>>> + * │ │ │
>>> + * │ ├─ P.U12 ───┼─ P.ROTX
>>> + * │ │ │
>>> + * │ │ ├─ P.INS
>>> + * │ │ │
>>> + * │ │ └─ P.EXT
>>> + * │ │
>>> + * │ ├─ P.LS.U12 ── P.PREF.U12
>>> + * │ │
>>> + * │ ├─ P.BR1 ───── P.BR3A
>>> + * │ │
>>> + * │ │ ┌─ P.LS.S0 ─── P16.SYSCALL
>>> + * │ │ │
>>> + * │ │ │ ┌─ P.LL
>>> + * │ │ ├─ P.LS.S1 ─┤
>>> + * │ │ │ └─ P.SC
>>> + * │ │ │
>>> + * │ │ │ ┌─ P.PREFE
>>> + * MAJOR ─┤ ├─ P.LS.S9 ─┤ │
>>> + * │ │ ├─ P.LS.E0 ─┼─ P.LLE
>>> + * │ │ │ │
>>> + * │ │ │ └─ P.SCE
>>> + * │ │ │
>>> + * │ │ ├─ P.LS.WM
>>> + * │ │ │
>>> + * │ │ └─ P.LS.UAWM
>>> + * │ │
>>> + * │ │
>>> + * │ ├─ P.BR2
>>> + * │ │
>>> + * │ ├─ P.BRI
>>> + * │ │
>>> + * │ └─ P.LUI
>>> + * │
>>> + * │
>>> + * │ ┌─ P16.MV ──── P16.RI ─── P16.SYSCALL
>>> + * │ │
>>> + * │ ├─ P16.SR
>>> + * │ │
>>> + * │ ├─ P16.SHIFT
>>> + * │ │
>>> + * │ ├─ P16.4x4
>>> + * │ │
>>> + * │ ├─ P16C ────── POOL16C_0 ── POOL16C_00
>>> + * │ │
>>> + * └─ P16 ─┼─ P16.LB
>>> + * │
>>> + * ├─ P16.A1
>>> + * │
>>> + * ├─ P16.LH
>>> + * │
>>> + * ├─ P16.A2 ──── P.ADDIU[RS5]
>>> + * │
>>> + * ├─ P16.ADDU
>>> + * │
>>> + * └─ P16.BR ──┬─ P16.JRC
>>> + * │
>>> + * └─ P16.BR1
>>
>> Nice ASCII tree! And you got it fits the 80 chars per line limit =)
>>
>
> Too bad we don't have a mark "Enjoyed-by:" ;).
There is an "Inspired-by:" although!
> Yes, it does fit 80 characters limit. It was created manually. I stumbled
> upon https://pythonhosted.org/asciitree/#ascii-trees the other day, but
> never used it, you may find it useful.
I'm tempted add it to the decodetree script...
> By the way, there is a serious science on creating such trees in the most
> compact or balanced way. See, for example, Reingold-Tilford algorithm
> ("Tidier Drawings of Trees", 1981).
Is this how nanoMIPS came with a rebalanced ISA?
Regards,
Phil.
- [Qemu-devel] [PATCH v7 12/14] tests/tcg: target/mips: Add tests for MIPS64R6 shift instructions, (continued)
- [Qemu-devel] [PATCH v7 12/14] tests/tcg: target/mips: Add tests for MIPS64R6 shift instructions, Aleksandar Markovic, 2019/03/04
- [Qemu-devel] [PATCH v7 10/14] tests/tcg: target/mips: Add tests for MIPS64R6 bit swap instructions, Aleksandar Markovic, 2019/03/04
- [Qemu-devel] [PATCH v7 11/14] tests/tcg: target/mips: Add tests for MIPS64R6 bit count instructions, Aleksandar Markovic, 2019/03/04
- [Qemu-devel] [PATCH v7 14/14] tests/tcg: target/mips: Add tests for MSA pack instructions, Aleksandar Markovic, 2019/03/04
- [Qemu-devel] [PATCH v7 08/14] tests/tcg: target/mips: Add wrappers for some MIPS64R6 instructions, Aleksandar Markovic, 2019/03/04
- [Qemu-devel] [PATCH v7 09/14] tests/tcg: target/mips: Add tests for MIPS64R6 logic instructions, Aleksandar Markovic, 2019/03/04
- [Qemu-devel] [PATCH v7 04/14] tests/tcg: target/mips: Add test utilities for 32-bit tests, Aleksandar Markovic, 2019/03/04
- [Qemu-devel] [PATCH v7 02/14] disas: nanoMIPS: Add graphical description of pool organization, Aleksandar Markovic, 2019/03/04
[Qemu-devel] [PATCH v7 03/14] tests/tcg: target/mips: Add wrappers for various MSA instructions, Aleksandar Markovic, 2019/03/04
[Qemu-devel] [PATCH v7 05/14] tests/tcg: target/mips: Add test utilities for 64-bit tests, Aleksandar Markovic, 2019/03/04
[Qemu-devel] [PATCH v7 01/14] disas: nanoMIPS: Correct comments to handlers of some DSP instructions, Aleksandar Markovic, 2019/03/04
[Qemu-devel] [PATCH v7 07/14] tests/tcg: target/mips: Extend functionality of MSA wrapper macros, Aleksandar Markovic, 2019/03/04
[Qemu-devel] [PATCH v7 06/14] tests/tcg: target/mips: Fix test utilities for 128-bit tests, Aleksandar Markovic, 2019/03/04
Re: [Qemu-devel] [PATCH v7 00/14] Misc target/mips fixes and improvements, Aleksandar Rikalo, 2019/03/05