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[Qemu-devel] [PATCH v3 08/10] target/arm: Implement ARMv8.5-CondM
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v3 08/10] target/arm: Implement ARMv8.5-CondM |
Date: |
Fri, 1 Mar 2019 12:04:59 -0800 |
Tested-by: Laurent Desnogues <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
v2: Update ID_AA64ISAR0.TS.
---
target/arm/cpu.h | 5 ++++
target/arm/cpu64.c | 2 +-
target/arm/translate-a64.c | 58 ++++++++++++++++++++++++++++++++++++++
3 files changed, 64 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index fc2909ea6d..a7aaec63d7 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3436,6 +3436,11 @@ static inline bool isar_feature_aa64_condm_4(const
ARMISARegisters *id)
return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0;
}
+static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2;
+}
+
static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index fcf79321e2..9fe0844a82 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -309,7 +309,7 @@ static void aarch64_max_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
- t = FIELD_DP64(t, ID_AA64ISAR0, TS, 1);
+ t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
cpu->isar.id_aa64isar0 = t;
t = cpu->isar.id_aa64isar1;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 49a09b58e3..c2b9e800c8 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1646,6 +1646,48 @@ static void handle_sync(DisasContext *s, uint32_t insn,
}
}
+static void gen_xaflag(void)
+{
+ TCGv_i32 z = tcg_temp_new_i32();
+
+ tcg_gen_setcondi_i32(TCG_COND_EQ, z, cpu_ZF, 0);
+
+ /*
+ * (!C & !Z) << 31
+ * (!(C | Z)) << 31
+ * ~((C | Z) << 31)
+ * ~-(C | Z)
+ * (C | Z) - 1
+ */
+ tcg_gen_or_i32(cpu_NF, cpu_CF, z);
+ tcg_gen_subi_i32(cpu_NF, cpu_NF, 1);
+
+ /* !(Z & C) */
+ tcg_gen_and_i32(cpu_ZF, z, cpu_CF);
+ tcg_gen_xori_i32(cpu_ZF, cpu_ZF, 1);
+
+ /* (!C & Z) << 31 -> -(Z & ~C) */
+ tcg_gen_andc_i32(cpu_VF, z, cpu_CF);
+ tcg_gen_neg_i32(cpu_VF, cpu_VF);
+
+ /* C | Z */
+ tcg_gen_or_i32(cpu_CF, cpu_CF, z);
+
+ tcg_temp_free_i32(z);
+}
+
+static void gen_axflag(void)
+{
+ tcg_gen_sari_i32(cpu_VF, cpu_VF, 31); /* V ? -1 : 0 */
+ tcg_gen_andc_i32(cpu_CF, cpu_CF, cpu_VF); /* C & !V */
+
+ /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */
+ tcg_gen_andc_i32(cpu_ZF, cpu_ZF, cpu_VF);
+
+ tcg_gen_movi_i32(cpu_NF, 0);
+ tcg_gen_movi_i32(cpu_VF, 0);
+}
+
/* MSR (immediate) - move immediate to processor state field */
static void handle_msr_i(DisasContext *s, uint32_t insn,
unsigned int op1, unsigned int op2, unsigned int crm)
@@ -1665,6 +1707,22 @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
s->base.is_jmp = DISAS_NEXT;
break;
+ case 0x01: /* XAFlag */
+ if (crm != 0 || !dc_isar_feature(aa64_condm_5, s)) {
+ goto do_unallocated;
+ }
+ gen_xaflag();
+ s->base.is_jmp = DISAS_NEXT;
+ break;
+
+ case 0x02: /* AXFlag */
+ if (crm != 0 || !dc_isar_feature(aa64_condm_5, s)) {
+ goto do_unallocated;
+ }
+ gen_axflag();
+ s->base.is_jmp = DISAS_NEXT;
+ break;
+
case 0x05: /* SPSel */
if (s->current_el == 0) {
goto do_unallocated;
--
2.17.2
- [Qemu-devel] [PATCH v3 00/10] target/arm: SB, PredInv, CondM, FRINT extensions, Richard Henderson, 2019/03/01
- [Qemu-devel] [PATCH v3 01/10] target/arm: Split out arm_sctlr, Richard Henderson, 2019/03/01
- [Qemu-devel] [PATCH v3 02/10] target/arm: Implement ARMv8.0-SB, Richard Henderson, 2019/03/01
- [Qemu-devel] [PATCH v3 05/10] target/arm: Add set/clear_pstate_bits, share gen_ss_advance, Richard Henderson, 2019/03/01
- [Qemu-devel] [PATCH v3 08/10] target/arm: Implement ARMv8.5-CondM,
Richard Henderson <=
- [Qemu-devel] [PATCH v3 04/10] target/arm: Split helper_msr_i_pstate into 3, Richard Henderson, 2019/03/01
- [Qemu-devel] [PATCH v3 07/10] target/arm: Implement ARMv8.4-CondM, Richard Henderson, 2019/03/01
- [Qemu-devel] [PATCH v3 03/10] target/arm: Implement ARMv8.0-PredInv, Richard Henderson, 2019/03/01
- [Qemu-devel] [PATCH v3 09/10] target/arm: Restructure handle_fp_1src_{single, double}, Richard Henderson, 2019/03/01
- [Qemu-devel] [PATCH v3 10/10] target/arm: Implement ARMv8.5-FRINT, Richard Henderson, 2019/03/01
- [Qemu-devel] [PATCH v3 06/10] target/arm: Rearrange disas_data_proc_reg, Richard Henderson, 2019/03/01
- Re: [Qemu-devel] [PATCH v3 00/10] target/arm: SB, PredInv, CondM, FRINT extensions, Peter Maydell, 2019/03/04