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[Qemu-devel] [PATCH 01/23] target/xtensa: implement PREFCTL SR
From: |
Max Filippov |
Subject: |
[Qemu-devel] [PATCH 01/23] target/xtensa: implement PREFCTL SR |
Date: |
Mon, 18 Feb 2019 22:10:49 -0800 |
Cache prefetch option adds an unprivileged SR PREFCTL. Add trivial
implementation for this SR.
Signed-off-by: Max Filippov <address@hidden>
---
target/xtensa/cpu.h | 1 +
target/xtensa/translate.c | 16 ++++++++++++++++
2 files changed, 17 insertions(+)
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index a01a94e2a683..4d8152682fe1 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -131,6 +131,7 @@ enum {
ACCLO = 16,
ACCHI = 17,
MR = 32,
+ PREFCTL = 40,
WINDOW_BASE = 72,
WINDOW_START = 73,
PTEVADDR = 83,
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 2fd64f8d995d..cbc52ecd8fa4 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -134,6 +134,7 @@ static const XtensaReg sregnames[256] = {
[MR + 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16),
[MR + 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16),
[MR + 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16),
+ [PREFCTL] = XTENSA_REG_BITS("PREFCTL", XTENSA_OPTION_ALL),
[WINDOW_BASE] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER),
[WINDOW_START] = XTENSA_REG("WINDOW_START",
XTENSA_OPTION_WINDOWED_REGISTER),
@@ -4152,6 +4153,11 @@ static const XtensaOpcodeOps core_ops[] = {
.par = (const uint32_t[]){MISC + 3},
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
+ .name = "rsr.prefctl",
+ .translate = translate_rsr,
+ .test_ill = test_ill_rsr,
+ .par = (const uint32_t[]){PREFCTL},
+ }, {
.name = "rsr.prid",
.translate = translate_rsr,
.test_ill = test_ill_rsr,
@@ -4777,6 +4783,11 @@ static const XtensaOpcodeOps core_ops[] = {
.par = (const uint32_t[]){MMID},
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
+ .name = "wsr.prefctl",
+ .translate = translate_wsr,
+ .test_ill = test_ill_wsr,
+ .par = (const uint32_t[]){PREFCTL},
+ }, {
.name = "wsr.prid",
.translate = translate_wsr,
.test_ill = test_ill_wsr,
@@ -5265,6 +5276,11 @@ static const XtensaOpcodeOps core_ops[] = {
.par = (const uint32_t[]){MISC + 3},
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
+ .name = "xsr.prefctl",
+ .translate = translate_xsr,
+ .test_ill = test_ill_xsr,
+ .par = (const uint32_t[]){PREFCTL},
+ }, {
.name = "xsr.prid",
.translate = translate_xsr,
.test_ill = test_ill_xsr,
--
2.11.0
- [Qemu-devel] [PATCH 00/23] tests/tcg/xtensa: conditionalize xtensa tests, Max Filippov, 2019/02/19
- [Qemu-devel] [PATCH 01/23] target/xtensa: implement PREFCTL SR,
Max Filippov <=
- [Qemu-devel] [PATCH 04/23] tests/tcg/xtensa: support configs with LITBASE, Max Filippov, 2019/02/19
- [Qemu-devel] [PATCH 02/23] tests/tcg/xtensa: indicate failed tests, Max Filippov, 2019/02/19
- [Qemu-devel] [PATCH 03/23] tests/tcg/xtensa: support configurations w/o vecbase, Max Filippov, 2019/02/19
- [Qemu-devel] [PATCH 06/23] tests/tcg/xtensa: fix endianness issues in test_b, Max Filippov, 2019/02/19
- [Qemu-devel] [PATCH 05/23] tests/tcg/xtensa: don't use optional opcodes in generic code, Max Filippov, 2019/02/19
- [Qemu-devel] [PATCH 07/23] tests/tcg/xtensa: enable boolean tests, Max Filippov, 2019/02/19
- [Qemu-devel] [PATCH 08/23] tests/tcg/xtensa: conditionalize debug option tests, Max Filippov, 2019/02/19
- [Qemu-devel] [PATCH 09/23] tests/tcg/xtensa: conditionalize cache option tests, Max Filippov, 2019/02/19
- [Qemu-devel] [PATCH 10/23] tests/tcg/xtensa: add straightforward conditionals, Max Filippov, 2019/02/19
- [Qemu-devel] [PATCH 16/23] tests/tcg/xtensa: conditionalize windowed register tests, Max Filippov, 2019/02/19