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[Qemu-devel] [PULL 13/27] hw/intc/armv7m_nvic: Allow byte accesses to SH
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 13/27] hw/intc/armv7m_nvic: Allow byte accesses to SHPR1 |
Date: |
Thu, 14 Feb 2019 19:05:49 +0000 |
The code for handling the NVIC SHPR1 register intends to permit
byte and halfword accesses (as the architecture requires). However
the 'case' line for it only lists the base address of the
register, so attempts to access bytes other than the first one
end up in the "bad write" default logic. This bug was added
accidentally when we split out the SHPR1 logic from SHPR2 and
SHPR3 to support v6M.
Fixes: 7c9140afd594 ("nvic: Handle ARMv6-M SCS reserved registers")
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
---
The Zephyr RTOS happens to access SHPR1 byte at a time,
which is how I spotted this.
---
hw/intc/armv7m_nvic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 790a3d95849..ab822f42514 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -1841,7 +1841,7 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr
addr,
}
}
break;
- case 0xd18: /* System Handler Priority (SHPR1) */
+ case 0xd18 ... 0xd1b: /* System Handler Priority (SHPR1) */
if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) {
val = 0;
break;
@@ -1956,7 +1956,7 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr
addr,
}
nvic_irq_update(s);
return MEMTX_OK;
- case 0xd18: /* System Handler Priority (SHPR1) */
+ case 0xd18 ... 0xd1b: /* System Handler Priority (SHPR1) */
if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) {
return MEMTX_OK;
}
--
2.20.1
- [Qemu-devel] [PULL 05/27] target/arm: Restructure disas_fp_int_conv, (continued)
- [Qemu-devel] [PULL 05/27] target/arm: Restructure disas_fp_int_conv, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 06/27] target/arm: relax permission checks for HWCAP_CPUID registers, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 07/27] target/arm: expose CPUID registers to userspace, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 08/27] target/arm: expose MPIDR_EL1 to userspace, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 09/27] target/arm: expose remaining CPUID registers as RAZ, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 10/27] linux-user/elfload: enable HWCAP_CPUID for AArch64, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 12/27] MAINTAINERS: Remove Peter Crosthwaite from various entries, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 15/27] target/arm: Rely on optimization within tcg_gen_gvec_or, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 19/27] target/arm: Remove neon min/max helpers, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 14/27] hw/arm/armsse: Fix miswiring of expansion IRQs, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 13/27] hw/intc/armv7m_nvic: Allow byte accesses to SHPR1,
Peter Maydell <=
- [Qemu-devel] [PULL 11/27] arm: Allow system registers for KVM guests to be changed by QEMU code, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 22/27] target/arm: Split out flags setting from vfp compares, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 18/27] target/arm: Use tcg integer min/max primitives for neon, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 23/27] target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR], Peter Maydell, 2019/02/14